A 1 GSa/s Deep Cryogenic, Reconfigurable Soft-core FPGA ADC for Quantum Computing Applications

Analog interfacing is the only way to communicate with a quantum processor, whether it is applying qubit operations or reading their quantum states. There exist other applications where analog interfacing is abundant, e.g. sensor networks, automotive, industrial control, etc. In those applications the use of FPGAs is continuously growing, however a direct link between the analog world and the digital FPGA is still missing (except for the newest generation of FPGAs, where analog-to-digital conversion is present, but limited in performance). External analog-to-digital converters (ADCs) are combined together with the FPGA to form a complete, application specific, system. This system is thus limited in compactness, exibility and reconfigurability. To address those issues we propose an ADC architecture, implemented entirely in a conventional FPGA, that is fully reconfifigurable and easy to calibrate. This allows one to alter the design, according to the system requirements. Therefore it can be used in a wide range of operating conditions, such as a harsh cryogenic environment, where we demonstrated that the FPGA is able to operate. This architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency, up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 8 bit resolution over a 0.6 to 1.9 V input range. The system non-linearities are less than 0.45 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.

Subject

ADC
FPGA
deep cryogenic
quantum computing
TDC

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http://resolver.tudelft.nl/uuid:04fadfcd-fb54-47c3-b564-661aefa40dda

Embargo date

2016-11-13

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Student theses

Document type

master thesis

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