Off-chip Self-timed SNN Custom Digital Interconnect System

Off-chip Self-timed SNN Custom Digital Interconnect System

Yang, Yichen (TU Delft Electrical Engineering, Mathematics and Computer Science)

van Leuken, T.G.R.M. (mentor)
Dalakoti, Aditya (mentor)
Frenkel, C.P. (graduation committee)

Delft University of Technology

Electrical Engineering | Circuits and Systems

2022-11-21

To support the spike propagates between neurons, neuromorphic computing systems always require a high-speed communication link.
Meanwhile, spiking neural networks are event-driven so that the communication links normally exclude the clock signal and related blocks. This thesis aims to develop a self-timed off-chip interconnect system with ring topology that supports multi-point communication in neuromorphic computing systems. This interconnect system is implemented in high-level modeling with SystemC and involves the burst-mode two-wire protocol in point-to-point communication. In order to ensure the flexibility of the system, the distributed control system is involved. Further, the system can be configured with different numbers of chiplets to fulfill various spiking neural network structures. We also explore optimization methods, which is a bi-directional ring topology achieving the growth of throughput. Based on evaluation and simulation results, the interconnect system can achieve 4.302Gbps with the specific application scenario.

Asynchronous link
SNN
Interconnect system
Ring topology

http://resolver.tudelft.nl/uuid:1154de0c-2cce-4aa4-bbb4-1c33869b33fd

2024-12-01

Student theses

master thesis

© 2022 Yichen Yang