A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support

A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support

Van Straten, J.

Wong, S. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

2016-05-25

This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance based on runtime information. The key challenge lies in translating this concept into actual working hardware. Note that reconfiguration must happen quickly for the increase in performance to outweigh the reconfiguration overhead. To accomplish this goal, a new processor and corresponding cache organization had to be developed, verified, and debugged. The dynamic reconfiguration concept used in the ρ-VEX processor is unique and, therefore, the following key components had to be designed: (1) a dynamic instruction cache that can service a single processor or multiple processors depending on the core configuration, (2) a dynamic data cache with coherency since we are dealing with multiple cores, (3) a reconfiguration control unit that synchronizes running threads before reallocating the computational and cache resources, and (4) a mechanism that allows state restoration after handling a trap. State restoration must be possible even if the configuration changed while the trap was being handled. This is an issue, because it is possible for a trap to interrupt a thread in intermediate states that would not normally occur in wider configurations. Reconfiguration takes only six clock cycles if there are no stalls from the memory subsystem, so overhead should be negligible. On top of the base design of the dynamic ρ-VEX processor, the following features were implemented: (1) variable-length instruction support to decrease instruction cache pressure, (2) a debugging peripheral and accompanying tools, and (3) a trace unit for offline debugging and cache performance logging. Furthermore, many parameters of the processor can be selected at design-time using generics, such as the issue width, the degree of reconfigurability, and the layout and availability of the computational resources. Additionally, the pipeline configuration, instruction set encoding, and control register functionality can be configured using a VHDL code generator. This work is intended to enable future research and development in dynamic processor design. It has already proven its value, as three MSc projects used the current design as a starting point, and four conference papers were published with results generated based on the current design. Finally, the processor will also serve as the basis for an ASIC design that is intended to be used in robotics and space applications.

r-VEX
dynamic reconfiguration
reconfigurable VLIW processor
reconfigurable cache
cache coherence
bus snooping
precise trap
precise interrupt
precise exception
external debug
self-hosted debug
variable-length instructions

http://resolver.tudelft.nl/uuid:115c94f1-a572-4c9d-b400-2eaf09102a2e

2018-05-18

Student theses

student report

(c) 2016 Van Straten, J.