On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture

On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture

Verbree, J.

Marinissen, E.J. (mentor)
Hamdioui, S. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

Computer Engineering

2011-11-04

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) is an emerging technology. It provides heterogeneous integration, higher performance and bandwidth, and lower power consumption. However, 3D-SICs suffer from lower compound yield, especially those based on Wafer-to-Wafer (W2W) stacking. In addition, testability of such devices is still in its infancy stage. This thesis addresses these two challenges. To improve the compound yield of W2W 3D-SICs, a technique known as wafer matching will be used. It defines the best matching of top and bottom wafers from repositories of pre-tested wafers. The simulation results show that the compound-yield increase depends on (1) the number of stack tiers, (2) the number of dies per wafer, (3) the die yield, and (4) the repository size. Moreover, they demonstrate that, for realistic cases, relative yield increases of 0.5% to 10% can be achieved. The thesis also proposes a three-dimensional Design-for-Test (3D-DfT) architecture that solves the testability issue of of 3D-SICs. The architecture is based on a modular approach, in which the various dies, their embedded IP cores, TSV-based interconnect, and external I/O can be tested as separate units, before and/or after bonding. Furthermore, the architecture leverages existing 2D DfT already present in the design, and adds a die-level wrapper based on IEEE Std 1500 augmented with additional features in order to be able to deals with 3D-SIC challenges (e.g., to transport signals up and down through the stack). The architecture is implemented and the simulation results show that it provides the flexibility and the modularity is realized at the cost of less than 0.1% area overhead when considering large industrial chips. The architecture could serve as a basis for further standardization of DfT for 3D-SICs.

3D-DfT
Test Architecture
Yield improvement
3D-SIC
TSV
Wafer matching

http://resolver.tudelft.nl/uuid:16cec059-45b2-4946-8291-b92b72db8913

2011-09-16

Student theses

master thesis

(c) 2011 Verbree, J.