This thesis has explored the possibility of using carbon nanotubes (CNT) as a novel material for through-silicon vias (TSV) in 3D-integrated circuits. With the steady downscaling trend of the semiconductor industry, a major limiting factor to the overall performance of the device is the delay from interconnects; a trend that is worsening over successive technology nodes. As a remedy to this, the industry has been exploring the possibility of fabricating three dimensional integrated circuits, with shorter interconnect lengths (hence delay). Even then, the standard interconnect (or via) material, which is copper, poses a host of physical and technological challenges that constrain the development of this technology. The carbon nanotube is considered to be a promising alternative to copper, which can alleviate most of these problems. The thesis investigated the LPCVD growth of CNT on a novel substrate, with Fe as catalyst layer and ZrN as support layer. The combination of these two materials has the potential to support the growth of ultra-long CNT vias that are ideal for TSV applications. Before the successful growth of CNT, however, the right growth recipe had to be identified. For this purpose, a design-of-experiments approach was followed and the Taguchi method was used to optimize the recipes. Using optimized recipes for the highest length, CNT growth on continuous and patterned catalyst islands were carried out, resulting in a super-growth of ~ 900 µm in the first case, and ~ 200 µm in the second. The difference in magnitude and uniformity of the growth height for the two cases was studied, and it was understood how the size and distribution of the catalyst islands played an important role in CNT growth. When fabricating CNT-based interconnects, one should also have an idea about their electrical properties. An important property is the resistivity, which needs to be lower than copper. During this work, a recipe was designed which could grow CNT with the minimum resistivity. In order to achieve this, two equivalent circuit models were studied and a simple model was developed, which could calculate the CNT resistivity from their physical parameters (quality, density, diameter etc.). To measure the values of these parameters, a series of characterization experiments were performed on the growth samples, and their resistivities were calculated. Seeing that, these values were orders of magnitude higher than copper, new recipes were designed to increase the CNT growth density and quality. Using these, it was possible to decrease the CNT resistivity. Finally, the designed recipes were put to the test, when integration of CNT as TSV was attempted in a real 3D-IC prototype. Although not entirely successful, the growth results so obtained, gave an indication of how CNT growth in deep vias could be performed, and the TSV process made successful in the future.