Radiation detectors are used in a large variety of fields such as medicine, security, defense, geophysics, industry and physics. They have been developed to detect the energy or position of radiation or charge particles. In Chapter 1 several X-ray detectors were introduced briefly. In gas filled X-ray detectors, incoming photons ionize inert gas and create electron and ions which can be collected at a thin wire anode inside of the chamber. The advantage of this type of detector is the possibility to amplify the signal or charge, hence a high signal to noise ratio. However, they suffer from low efficiency for X-ray detection due to low density of the filled gas. In scintillation detectors, X-ray photons collide with the scintillator and create UV or visible light which can be converted into an electrical signal by a photodiode. The main disadvantage of scintillation detectors is their poor energy resolution due to a large amount of loss, and the relatively high ionization energy, i.e. 20-500eV. In semiconductor detectors, electron and hole pairs (EHPs) can be generated at much lower energies than gas filled detectors. The possibility to measure both position and energy of incoming radiation accurately is a unique property for semiconductor detectors. However, they do not have any intrinsic signal gain, as is the case in gas filled detectors. Therefore an integrated or external amplifier is required for this type of detector. When selecting semiconductor materials, higher density, a higher atomic number for better absorption efficiency, lower bandgap for better resolution, higher mobility for fast detection beside lower leakage current, and a thicker substrate should be considered. Among different semiconductor materials, silicon is an interesting material for X-ray detectors because of the availability of fabrication process technology, lower cost and possibility to integrate advanced electronic circuits and further signal processing. PIN photodiodes made in a high resistivity silicon substrate are the simplest, cheapest, commercially available type of X-ray detectors where the full thickness of silicon is depleted by reverse bias to extract the generated EHPs with radiation. However, PIN detectors have a large anode area which makes the output capacitance so large that higher noise level in the output is the result. In Si(Li) and Ge(Li) detectors, crystals of silicon or germanium are used with thicknesses in the range of a few mm to cm. To obtain intrinsic material (concentration levels as low as 109 cm-3) for complete thickness, a Li drifting process is used where Li acts as a donor to compensate acceptor ions. The typical biasing voltage is 500V to 4000V. In order to prevent redistribution of the Li atoms, the detector has to be kept at a low temperature with liquid nitrogen, which is the main disadvantage for this type of detector. Silicon strip detectors offer 2D position sensitive detection. They are similar to PIN diodes, but the p+ region is divided into many strips on the front side to collect the holes, and the n+ region is divided into many n+ strips on the backside to collect the electrons. In silicon pixel detectors (SPDs) only one side of p+n is patterned and every pixel has its own readout electronics attached to the pixel by solder bumping. In p-n CCDs the drift function is carried out by reverse and forward biases of p-n junctions in periodic cycles by external pulses acting as series of shift registers drifting the electrons toward the anode. Silicon drift detectors (SDDs) are detectors with an extremely small anode and low output capacitance, thus less noise and high energy resolution. In a circular configuration the p+ drift rings create an electric field parallel to the surface to collect the electrons in the small anode region. Independent of the active area of the detector, a typical output capacitance of an SDD is in the range of 60fF. On-chip electronic devices are placed on the front side to amplify the signal. In the Silicon Drift Detector Droplet (SD³) the anode and integrated transistor are moved to the margin of the structure where they can be shielded from direct radiation by a proper collimator. This has a significant effect on the low energy background in the SDD. With the SD³ the peak/background ratio is increased from 3000 to 5000. Multichannel SDDs consist of many single SDDs with individual readout but a common entrance window, guard ring and supply voltage where the sensitive area is very big, up to few cm2, without losing the energy resolution and count rate capability of the single SDD. Finally in 3D detectors implanted electrodes of conventional SDD are replaced with a 3D array of p+ and n+ electrodes inside the silicon. In 3D detectors collection distances and times are about one order of magnitude less than planar strips and pixel detectors, and the depletion voltage is about two orders of magnitude lower. However, the fabrication process is complex and expensive. In Chapter 2 the properties of the boron layer were described in detail. A boron layer is deposited in an ASM Epsilon reactor using Diborane (B2H6) and Hydrogen as a dopant gas and carrier gas at temperatures ranging from 500oC to 700oC. The typical thickness of the boron layer deposited at 700oC for a 7min deposition time is equal to a 2-3nm uniform layer. Deposition at lower temperatures results in a non-uniform boron layer which is confirmed by TEM analysis. Fabricated PureB diodes behave like a conventional deep p+-n junction with near ideal ideality factors lower than ? 1.02, and low saturation current. Resistors are key elements in integrated circuits and can be made with a p-n junction or by poly silicon deposition. However, drawbacks for these two technologies are bias dependence, high parasitic capacitance for high Ohmic values in junction made resistors, and large variation and process dependency for poly-made resistors. The typical sheet resistance value of the deposited boron layer is in the 100k?/? range which can be changed by deposition time, temperature and annealing. In this thesis, the photodiodes were fabricated on high-resistivity Si (HRS) <100> wafers, n-type phosphorous-doped to 2-10k?-cm. The resistors were also placed directly in the HRS so that associated depletion layers were tens of microns wide even at 0V biasing. Thus the voltage dependence of the resistance value is negligible. The fabrication process consisted of oxidation followed by etching, boron layer deposition and finally metallization. To remove Al from the top of the boron layer, a combination of dry etching and short wet etching in diluted HF was used. The sheet resistance values extracted from measurement of the ring structures are 2.5×104 ?/? for a 7min 700oC deposition and 3.8×105 ?/? for a 20min 500oC deposition. Fabricated resistors show high linearity in voltage ranges between 10V and 100V and are stable in temperature ranges from 15°C to 95°C. The 500oC resistors have a TCR (temperature coefficient of the resistor) less than 200ppm/oC up to a measurement temperature of 70oC, then increasing to around 1000ppm/oC at 95oC. The TCR of the 700oC sample had an almost constant value of less than 400 ppm/oC over the whole measurement temperature range. The measured leakage current was less than 1nA/cm2 at 10V reverse bias over all dies of the 100mm wafer. The measured resistor tolerance was in the range of 1% to 5% for both k? and M? resistors. Since Pure Al can short the shallow junctions to bulk especially when the boron layer is deposited at lower temperatures (non-uniform boron layer) or when there is a defect on the substrate, an alloy of AlSi (1% Si) is used. However, removing AlSi with a wet process is not compatible with the boron layer process. Therefore it is better to add a diffusion barrier layer between the Al and boron layer. Among different studied diffusion barrier layers such as Ti, TiN, AlN and ZrN, only ZrN showed better process compatibility and no influence on the electrical performance of the detectors. Optical and SEM inspections show a defect-free detector surface when using 10nm ZrN between the Al and boron layer for both the 700oC and 500oC deposited layers. As an alternative, a lift-off process was developed to prevent any Al residuals on the boron layer. After PureB layer deposition at 700oC or 500oC, a negative photoresist (AZ®nLOF) was applied and patterned followed by 400nm-thick Al layer deposition by evaporation. Then the resist was stripped in acetone or a NMP solution in an ultrasonic bath. For both PureB layers deposited at 700oC or 500oC, the lift-off process was successfully performed. However, the limitation of Al thickness and the deposition method (evaporation) can be a challenge for some applications. In Chapter 3 the working principle of SDDs was reviewed. They have a higher count rate and better energy resolution with respect to other X-ray detectors. In order to have a successful working detector, different aspects of SDDs must be selected, designed and simulated carefully. The starting material for SDDs is high-Ohmic silicon wafers due to a better carrier lifetime (in the order of milliseconds) and lower required voltage for full depletion. To obtain better wafer uniformity typically wafers are made with the Neutron Transmutation Doped (NTD) method where uniformity of the phosphorus doping is achieved by exposing an ingot of high-purity silicon to a uniform flux of thermal neutrons. For detection of higher energies, thicker wafers should be used. Furthermore, a <100> silicon substrate has a higher charge collection efficiency (CCE) of soft X-rays (below 200nm wavelengths) and has a lower surface leakage current compared to the <111> orientation. The entrance window of the detector determines the lowest energy the detector can detect. In SDDs the entrance window is kept in a vacuum by using Beryllium or polymer windows. Those windows can limit the lower range of detectable X-rays. In TEM systems a very high vacuum condition exists, thus those windows are not required. Therefore the lower detectable range can be reduced. In order to detect even lower X-rays energies (few hundred eVs), the dead layer of the p+ region in the entrance window should be as thin as possible, i.e. a shallow junction is required. A typical dead layer of 40nm by implantation is reported. To keep full depletion in the center of detector, the entrance window is biased at Vdep which corresponds to a depletion voltage of the full wafer thickness. In the outer drift ring the applied voltage is equal to 2Vdep to ensure enough drift potential for the electrons towards the anode. Leakage current is a very important parameter in the SDDs which defines noise level. Bulk leakage current can be reduced by selecting a high quality wafer and lowering the process temperature. Surface generation leakage current can originate from processing defects and interface states generated in the bandgap region near the surface by abrupt discontinuity in the silicon interface. A sink anode is a structure to reduce the surface leakage current by providing a path to drain away the surface electrons through the p+ field electrodes. In order to improve the energy resolution as much as possible, total capacitances including anode capacitance and stray capacitance (connection path to the external circuit), should be equal to the input capacitance of the external amplifier. A guard ring structure maintains low leakage current for the SDD without any breakdown at high voltage biases for depletion and drift mechanisms. The entrance window can be made from a PureB layer which has only a 2nm-thick dead layer for the p+ layer. Therefore measuring lower energies (as low as 100eV) should be possible. Furthermore, PureB made resistors can be used as voltage dividers in the drift region of the detectors. A continuous layer of boron can act as a distributed resistor to drift the electrons toward the anode. However, calculations and simulations showed one layer of boron cannot generate enough electric field to drift the electrons. The inner part has a higher resistance than outer part; therefore the electric field is concentrated only in the center of the detector and there is no force on the electrons to drift them to the anode. For the designed detector with an inner radius of 135?m and outer ring radius of 3135?m using the boron layer with a sheet resistance value of 105?/?, the total resistance between the contact pads is equal to 50k?. Yet 95% of this value is concentrated only in a 135?m to 500?m region of the detector. The electric field is around three orders of magnitude less in the outer ring thus it is only effective at the inner side of the detector; there is not enough electric field to move the electrons toward the anode in the outer sides of the detector. Potential distribution shows at a 40V applied voltage, electrons will be accumulated in the gutter, the minimum of the potential energy, and will be moved slowly to the anode. At 160V, the drift voltage slope along the detector surface is lightly sharper than the 40V case but still too small to drift the electrons toward the anode. Therefore around 80% of the drift area has an almost zero electric field. However, a dual boron layer with two different sheet resistances and a special design can create a constant electric field in the drift region while the leakage current is still low. In this design the whole surface covered with two layers of boron to have minimum leakage current where the low sheet resistance layer is denser near the anode, and the high sheet resistance layer is denser in the outer rings to produce a constant resistance and electric field over the drift area. Chapter 4 describes designing a guard ring structure and integrating an on-chip amplifier for SDDs where there is no multiplication mechanism. Consequently an on-chip or off-chip amplifier is necessary. With on-chip amplification, undesirable interference effects related to wire bonding, such as stray capacitance and microphonic noise, can be avoided. To select the type of transistor for the SDD, a JFET is preferred because of noise considerations. Bipolar transistors have higher shot noise and CMOS transistors have a higher 1/f noise component. In designing the JFET there is a trade-off between obtaining minimum noise and minimum capacitance while keeping the transconductance (gm) as high as possible. Gate capacitance plays an important role in this trade-off. Since mobility of an nFET is higher, it offers a higher cut-off frequency than a pFET. For optimum SDD resolution, input capacitance of the JFET is equal to detector’s capacitance. In a SDD typically the JFET is placed inside the anode, which is isolated by a p-type region. The anode is connected to the gate, in the common source configuration the drain is connected to the power supply, and the source is connected to the external circuit. Accumulated charges on the anode can be discharged by reset devices such as a diode, JFET or MOSFET. Availability of technology and layout compatibility, minimum added noise and maximum linearity determine the choice of the reset transistor. In this thesis two types of on-chip JFET structures with a 4.5?m gate length together with different reset devices were designed for SDDs. The reset devices were embedded either in the JFET or in the small anode region. The parasitic capacitor between the detector anode and the transistor guard ring can act as a feedback capacitor. In the fabrication process flow, in order to find the optimum implantation parameters (energy and dose) for the gate (p+), S/D (n+) and deep n- and deep p-regions, two different routes were investigated. For gate doping, a combination of boron implantation and boron layer deposition was used. Moreover in this chapter designing multi-guard ring structures was discussed. According to electrical measurements at different temperatures, a positive temperature coefficient for the breakdown voltage was found, which means the breakdown mechanism is an avalanche type. To prevent breakdown, several multi-guard ring structures were studied. Multi-guard ring structures consist of a conventional large p-type guard (240?m width), a series of intermediate concentric circular p-type guard rings (with different pitches, widths and metal overlap of the field plate), and a large n+-type guard (150?m width) near the scribing line. The function of the n+ guard ring is to shield any existing positive charges in the oxide and prevent extension of depletion region toward the dicing line. As a result, the leakage current drops significantly. In this structure, parameters such as gap size, oxide charge, bulk doping concentration and field plate (metal extension) design have influence on the potential distribution of the guard rings. One of the designed structures works up to the limit of the measurement systems (1100V) with very low leakage current in the range of 1.5-3nA/cm2. In this structure the width of the guard rings was 25?m, the first gap (between the large guard and first intermediate guard ring) was 35?m, and the pitch was 80?m for the rest of the rings, with an inward field plate extending 5-30?m. Other structures show a roughly 400V breakdown voltage. According to the measurements of different designed guard ring structures, a gap of around 40?m is an optimal value for the distance between the large guard ring and first ring of the multi-guard structure. Moreover, it was found that a field plate in the inward direction offers a higher breakdown voltage because of charge shielding. In Chapter 5 the fabrication process and characterization results of SDDs were discussed. Since processing is performed on both sides of the wafers, special care should be considered during the processing steps such as wafer handling, implantation and wet etching in order to prevent any damage to the other side of the wafer. Furthermore, since the carrier lifetime is very important in SDD performance, high temperature processing steps should be avoided as much as possible. Therefore activation of dopants, particularly in case of JFET integration, at lower temperatures can be a challenge. In general a typical fabrication process flow starts with dry oxidation followed by guard ring and anode implantations by boron and phosphorous dopants. The next step is TEOS oxide deposition and annealing. Then the oxide layer is etched to open the regions for boron deposition to create p+ regions. Boron deposition is selective which means it deposits only on silicon. Al metallization on both sides is the next step. In order to etch Al and expose the boron layer a combination of dry (keeping the dimensions same as the design) and wet etching in diluted HF (to land on the boron layer without damaging it) is performed. Alloying in forming gas is the last step to create Ohmic contact of doped silicon with Al. For the double boron layer process flow, two reticles (litho steps) are used before boron deposition. Using the first litho step, oxide was etched in the drift region to leave a 30nm-thick oxide. With the second litho step, a 30nm-thick oxide was etched from low sheet resistance areas. A low sheet resistance boron layer was deposited and followed by a 10sec BHF step to etch a 30nm-thick oxide from the rest of drift region. The previously deposited boron layer is not attacked by this short BHF step. At the end, high sheet resistance boron layer was deposited. In the process flow for JFET integration there are several implantation steps for deep p, deep n, S/D and gate regions. Fabricated wafers were subjected to electrical measurement to characterize the wafer quality and fabricated SDDs. Measurement and calculation of the doping profile from CV curves result in 144.5µm and 217.5µm depletion depths on the entrance window side and device side of the silicon wafer, respectively. This measurement reveals that the entrance window (front side) of the wafer has a lower resistivity than the device side (backside). Knowledge of the bulk generation lifetime (?g) and surface generation velocity (sg) of the wafer is essential for process control and radiation-damage monitoring in radiation detectors. Using the designed gated diode structures, ?g and sg can be extracted. The gate area (Ag) is 0.3 mm2-1.5 mm2 with a gate length (Lg) of 95-470?m. During the measurement, the diode is kept at a constant reverse voltage (Vd) while the changes of the diode current are monitored when the gate is swept from accumulation toward the inversion. I-V measurement was done on 12 samples for each gate length, then using the bulk and surface generation currents and depletion region formulas, ?g and sg were extracted. The average value of the bulk generation lifetime was 40ms and surface generation velocity was 2.1cm/s for the fabricated wafers. Furthermore, the boron layer is used as a voltage divider between the inner and outer rings. The resistors made with 500oC and 700oC PureB layers are stable in different locations in the wafer with a maximum tolerance of 1.7% over the wafer for high temperature samples compared to 4.9% for low temperature samples. The resistors made with implantation in general have more fluctuation over the wafer. The calculated value of the tolerance for resistors made with implantation is 30% (only working devices were considered) while for resistors made with 500oC PureB it is only 4.9% (all devices were working). A thicker passivation layer leads to a lower leakage current. For boron layer SDDs there is no difference in the leakage current between oven and Epsilon annealing suggesting a lower thermal budget process using an Epsilon reactor with a very short time. Having field plate (metal overlap on the oxide) which covers the oxide in the drift rings of the SDD reduces the leakage current by factor of two. Using the double boron layer process, the leakage current was lower than the single boron layer process. The explanation can be that second boron layer introduces a layer of holes which suppresses the minority carrier’s currents resulting in a very low leakage current. Finally leakage current of the continuous design (one boron layer) and constant field design (double boron layer) are around 6 and 20 times lower than a conventional SDD, respectively. Since measuring the JFET in SDD structure is not possible (gate is connected to the anode) at the wafer level, individual JFET structures were placed in the layout with similar dimensions as SDD JFETs. The length of transistor is L=4.5?m and the width is W=48.5?m with the saturation current equal to 412.5?A, transconductance (gm) equal to 198.65?A/V at a drain voltage of 4V, a gate voltage of zero volts, pinch-off voltage of -4V and gate capacitance of 71.48fF. At the end of the chapter a novel interposer is introduced to measure the devices with contact pads on both sides. In this interposer, the device is mounted on the center hole and there are TSV-type connections in the periphery of the center hole. With wire bonding, contact pads are connected to the TSV connections to transfer all pads to one side. In order to protect the wire bonds, a Teflon cavity was developed. Therefore all contact pads are available for measurement from the top side of the complete package. Using this developed package we could do all DC and CV measurements on the probe station successfully.