On-chip output stage design for a continuous class-F power amplifier

On-chip output stage design for a continuous class-F power amplifier

Kumaran, A.K. (TU Delft Electronics)
Pashaeifar, M. (TU Delft Electronics)
D'Avino, Marco (Catena)
de Vreede, L.C.N. (TU Delft Electronics)
Alavi, S.M. (TU Delft Electronics)

2021

Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2^nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2^nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.

Common-mode analysis
Continuous class F (CCF)
Differential-mode analysis
Harmonic termination
Output matching network
Power amplifier (PA)

http://resolver.tudelft.nl/uuid:31978174-0bf1-4206-a471-7432b530aad8

https://doi.org/10.1109/ISCAS51556.2021.9401788

Institute of Electrical and Electronics Engineers (IEEE), Piscataway

2022-01-09

978-1-7281-9201-7

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, 2021-05-22 → 2021-05-28, Virtual at Daegu, Korea, Republic of

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Institutional Repository

conference paper

© 2021 A.K. Kumaran, M. Pashaeifar, Marco D'Avino, L.C.N. de Vreede, S.M. Alavi