Power-Efficiency Analysis of Accelerated BWA-MEM Implementations on Heterogeneous Computing Platforms

Power-Efficiency Analysis of Accelerated BWA-MEM Implementations on Heterogeneous Computing Platforms

Houtgast, E.J. (TU Delft Computer Engineering; Bluebee, Rijswijk)
Sima, V.M. (Bluebee, Rijswijk)
Marchiori, G. (Bluebee, Rijswijk)
Bertels, K.L.M. (TU Delft Quantum & Computer Engineering; TU Delft FTQC/Bertels Lab)
Al-Ars, Z. (TU Delft Computer Engineering)

Athanas, Peter (editor)
Cumplido, René (editor)
Feregrino, Claudia (editor)
Sass, Ron (editor)

Quantum & Computer Engineering

2016-12

Next Generation Sequencing techniques have dramatically reduced the cost of sequencing genetic material, resulting in huge amounts of data being sequenced. The processing of this data poses huge challenges, both from a performance perspective, as well as from a power-efficiency perspective. Heterogeneous computing can help on both fronts, by enabling more performant and more power-efficient solutions. In this paper, power-efficiency of the BWA-MEM algorithm, a popular tool for genomic data mapping, is studied on two heterogeneous architectures. The performance and power-efficiency of an FPGA-based implementation using a single Xilinx Virtex-7 FPGA on the Alpha Data add-in card is compared to a GPU-based implementation using an NVIDIA GeForce GTX 970 and against the software-only baseline system. By offloading the Seed Extension phase on an accelerator, both implementations are able to achieve a two-fold speedup in overall application-level performance over the software-only implementation. Moreover, the highly customizable nature of the FPGA results in much higher power-efficiency, as the FPGA power consumption is less than one fourth of that of the GPU. To facilitate platform and tool-agnostic comparisons, the base pairs per Joule unit is introduced as a measure of power-efficiency. The FPGA design is able to map up to 44 thousand base pairs per Joule, a 2.1x gain in power-efficiency as compared to the software-only baseline.

read mapping
FPGA
GPU
Next Generation Sequencing
power-efficiency

http://resolver.tudelft.nl/uuid:31d95525-9eba-498e-8900-69e80f60b4ce

https://doi.org/10.1109/ReConFig.2016.7857181

IEEE, Danvers, MA

978-1-5090-3707-0

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, 2016-11-30 → 2016-12-02, Cancun, Mexico

Accepted Author Manuscript

Institutional Repository

conference paper

© 2016 E.J. Houtgast, V.M. Sima, G. Marchiori, K.L.M. Bertels, Z. Al-Ars