Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology

Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology

Kumar, P.

Charbon, E. (mentor)
Bogdan Staszewski, R. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

2011-09-09

The interest in high performance three-dimensional (3D) imaging has grown in recent years due to immense demand in engineering, science, medicine and entertainment domains. The driving goals of state-of-the-art 3D imagers are high sensitivity to light and fine depth resolution at long range. Furthermore, high level of integration is desirable to achieve low system cost. To meet these demands, the industry has started to transition from traditional analog techniques to standard CMOS based solutions. In this thesis, a novel time-of-flight 3D CMOS imager is proposed. The focus of the design is low power consumption while maintaining human-eye safety requirements. The imager targets security applications, primarily facial recognition, but is also suitable for automotive vision and robotics. In this work, a prototype of a 32x32 pixel array is designed, where each pixel consists of a single-photon avalanche diode as photodetector and a time-to-digital converter (TDC) for fast image acquisition. The imager is expected to achieve millimeter-level depth resolution for range as long as 30 m and has a maximum frame-rate of 1000 fps. Each pixel is constructed within 25x25 ?m2 area and has a fill factor of 5.76%. The layout implementation has been carried out in a 65 nm CMOS technology and would be the first of its kind at this process node.

3D Imaging
SPAD
TDC
65nm Pixel Array

http://resolver.tudelft.nl/uuid:340a1ab8-c9b6-443f-9f7c-122a3b61f4e6

2012-12-31

Student theses

master thesis

(c) 2011 Kumar, P.