Print Email Facebook Twitter Hardware Algorithms For Tile-Based Real-Time Rendering Title Hardware Algorithms For Tile-Based Real-Time Rendering Author Crisu, D. Contributor Sips, H.J. (promotor) Faculty Electrical Engineering, Mathematics and Computer Science Department Computer Engineering Date 2012-05-01 Abstract In this dissertation, we present the GRAphics AcceLerator (GRAAL) framework for developing embedded tile-based rasterization hardware for mobile devices, meant to accelerate real-time 3-D graphics (OpenGL compliant) applications. The goal of the framework is a low-cost, low-power, high-performance design that delivers good image quality. We focus on several key problem areas in tile-based rasterization, such as: rasterization and triangle traversal, antialiasing, and geometrical primitive list sorting. We present an original triangle traversal hardware algorithm implementation, composed of a systolic primitive scan-conversion subsystem and a logic-enhanced memory subsystem, able to deliver 4 pixel positions per clock cycle in a very advantageous spatial pattern, exploited to reduce the power consumption and increase the throughput, to the pixel processing pipelines for rasterization. Area-sampling antialiasing is achieved with a pixel-coverage mask generation algorithm that reduces the mask storage costs by exploiting the quadrant symmetry property when deriving on the fly, via computationally inexpensive operations, the required coverage masks. The costs are reduced by an order of magnitude and the image quality, i.e., coverage mask accuracy, almost doubles when compared to prior state-of-the-art implementations. At the front end of the rasterization process, as the host processor needs to be able to process different other system tasks in a system-on-chip embedded architecture, we propose a novel and efficient hardware primitive list sorting algorithm that lowers on the one hand the effort of the host processor required to generate the primitive tiling lists and reduces on the other hand the external memory traffic. For an implementation footprint similar to an 8KB SRAM memory macro, the number of the instructions on the host processor for tiling list generation was lowered by 4–9x and the memory cost by 3–6x, for our embedded benchmark suite GraalBench, when compared to the software driver implementation alone. Our estimations indicate that the GRAAL design, clocked at a frequency of 200MHz, can sustain a rendering and fill rate of 2.4 million triangles/s and 460 million pixels/s for typical 3-D graphics scenes. Subject 3-D graphics algorithms and architecturestile-based rasterizationembedded systemslow-power circuitscomputer arithmetic To reference this document use: http://resolver.tudelft.nl/uuid:3cec89f0-9a2e-4a09-a015-6a7f30ac0c96 Publisher Koninklijke Bibliotheek, Den Haag ISBN 9789072298263 Part of collection Institutional Repository Document type doctoral thesis Rights (c) 2012 Crisu, D. Files PDF dan_crisu_PhD_thesis.pdf 2.38 MB Close viewer /islandora/object/uuid:3cec89f0-9a2e-4a09-a015-6a7f30ac0c96/datastream/OBJ/view