Print Email Facebook Twitter Hierarchical Memory Diagnosis Approach Title Hierarchical Memory Diagnosis Approach Author Jain, V.R. Contributor Hamdioui, S. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Computer Engineering Date 2011-07-19 Abstract Semiconductor memories are an inherent part of many modern electronic systems. Due to the fast development of memory process technology and the escalating computing speeds, the on-chip share of memories is rapidly increasing. Additionally, the quality and reliability requirements are becoming more severe especially for critical applications such as automotive and aerospace. Zero defect per million level is now a reality. To satisfy the quality constraints, it is vital to investigate the failure mechanisms. Also, it is required to address the problem of continually decreasing memory yield. Low yield is one of the major threats of the miniaturized electronic systems. Desire for high yield along with the stress to decrease the time to market, has heightened the importance of memory fault diagnosis. The traditional ways of fault diagnosis are not adequate for covering the entire memory fault scope. They suffer from various drawbacks like high complexity, high cost, platform dependence and limited scope. There is a need to introduce changes to the fundamental principles of memory testing and diagnosis approaches. This thesis presents a novel memory fault diagnosis approach which accurately identifies the faulty memory block and determines the fault type. The proposed approach is platform independent, based on a hierarchical methodology and incorporates several innovative ideas and algorithms. It builds upon the concepts of Test Primitives, Test Classes and Design for Diagnosis. The strength of Hierarchical Memory Diagnosis approach lies in the fact that, unlike conventional approaches, there are no specific implementation requirements other than running a test and determining the pass/fail status of the applied diagnostic test. The scope of the target faults includes all static and dynamic faults occurring in all parts of the memory system. The new approach contributes to the acceleration of characterization of possible defect mechanisms responsible for yield loss in the emerging technologies. Subject diagnosisDfDMarch testsmemorySRAMSRAM simulation To reference this document use: http://resolver.tudelft.nl/uuid:3f677e31-aa91-4641-a7a2-db8295ffa5fd Embargo date 2015-07-19 Part of collection Student theses Document type master thesis Rights (c) 2011 Jain, V.R. Files PDF Thesis_Vishwas.pdf 3.83 MB Close viewer /islandora/object/uuid:3f677e31-aa91-4641-a7a2-db8295ffa5fd/datastream/OBJ/view