A Low Power 10-bit SAR ADC in a 45nm CMOS process

A Low Power 10-bit SAR ADC in a 45nm CMOS process

Dyachenko, V.A.

Makinwa, K.A.A. (mentor)

Electrical Engineering, Mathematics and Computer Science

ELlectronic Instrumentation Laboratory

2012-11-02

In this work a low power SAR ADC with 8.9 ENOB for wireless communication systems is presented. A capacitive charge redistribution DAC with a unit capacitor of 0.5fF is used. The implemented charge-sharing technique, allows the use of 2^(N-1) + 1 unit capacitors, instead of the conventional 2^N , thus decreasing the DAC area and the DAC switching power by a factor of 2. An asynchronous digital controller eliminates the need of an external high frequency clock. The test chip has been manufactured in a CMOS 45nm process. The measured power consumption is only 45µW at the sampling rate of 16MS/s. The total area of the ADC is only 0.01mm2 . The achieved FoM of 5.9fJ/conv is comparable with state-of-the art.

ADC
low power
charge sharing
charge redistributing
SAR
CMOS
low voltage
asynchronous

http://resolver.tudelft.nl/uuid:407e656f-30b6-4694-a7b3-19631892ceea

2013-06-01

Student theses

master thesis

(c) 2012 Dyachenko, V.A.