Print Email Facebook Twitter A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC Title A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC Author Zhan, Xin (TU Delft Electrical Engineering, Mathematics and Computer Science) Contributor Sebastiano, Fabio (mentor) Bolatkale, Muhammed (mentor) Cenci, Pierluigi (mentor) Degree granting institution Delft University of Technology Date 2018-09-21 Abstract This thesis presents the design and implementation of a low power 3rd-order loop filter and a low power, compact, high-speed inverter-based amplifier designed in 28nm HPC for a GHz sampling Σ∆ modulator.In the earlier design, the size of the pMOS in an inverter was found to be nine times larger than the nMOS which is not practical to obtain a compact design.The proposed 4by4 inverter structure in a kind of matrix form achieves a gain of minimum 25dB and maximum 28dB at the worst corner and best corner without loading resistor respectively. The designed inverter amplifier is found to be relatively tolerant over PVT without an LDO. The simulation of the modulator system is implemented with an ideal quantizer and resistive DAC. The simulation results of the modulator shown an ENOB of 10bits with 0.41mW power consumption in the worst case and an ENOB of 10.7bits with 0.53mW power consumption in the best case. Subject Sigma DeltaADCloop filter To reference this document use: http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652 Part of collection Student theses Document type master thesis Rights © 2018 Xin Zhan Files PDF Master_thesis_Xin_Zhan.pdf 5.53 MB Close viewer /islandora/object/uuid:40957c09-3edd-474c-b271-f67bda41d652/datastream/OBJ/view