Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

Tohidian, M.; Madadi, I.; Staszewski, R.B.

doi:doi:10.1109/JSSC.2014.2359656

Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

Title

Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

Author

Tohidian, M.
Madadi, I.
Staszewski, R.B.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Date

2014-10-13

Abstract

In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/$surd$ Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm 2.

Subject

CMOS
IIR
digital equalization
discrete time
high linearity
high order
low noise
low power
low-pass filter
passive
real pole
reconfigurable
switched capacitor