An Ultra-Low-Power ADPLL for WPAN Applications

An Ultra-Low-Power ADPLL for WPAN Applications

Chillara, V.K.

Staszewski, R.B. (mentor)
Liu, Y.H. (mentor)
Vidojkovic, M. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics

2013-11-15

RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios. Compared to analog PLLs, all-digital phase-locked loops (ADPLLs) are preferred in nanoscale CMOS, as they offer benefits of smaller area, programmability, capability of extensive self-calibrations, and easy portability. However, analog PLLs dominate the ulp arena, since the time-to-digital converter (TDC) of an ADPLL has traditionally been power hungry. In this work [1], an ultra-low power 2.1 GHz – 2.7 GHz fractional-N ADPLL is presented for wireless personal area network (WPAN) applications. A DTC-assisted snapshot TDC and a DC-coupled DCO buffer with a tunable voltage transfer characteristic (VTC) are proposed to lower the power consumption. The ADPLL prototype fabricated in TSMC LP 40 nm CMOS process consumes only 860 µW at 1 V supply, and has a measured rms jitter of 1.71 ps (integrated from 1k to 100MHz), leading to a state-of-the-art jitter -power FoM of -236 dB. The frequency modulation capability is also demonstrated with a 2 Mcps HS-QPSK modulation for IEEE 802.15.4 (ZigBee) and 1 Mbps GFSK for Bluetooth Smart. This work presents the first-ever wireless ADPLL to break the 1mW barrier and consumes at least five-times lower power compared to state-of-the-art ADPLLs. The presented low-power techniques enable the adoption of ADPLLs in the emerging ultra-low-power applications.

ADPLL
frequency synthesis
ultra-low-power

http://resolver.tudelft.nl/uuid:53911767-cf72-4441-885b-d3dc6b7949d8

2014-11-15

Student theses

master thesis

(c) 2013 Chillara, V.K.