A Digital-Intensive Wakeup Timer based on an RC Frequency-Locked Loop for Internet-of-Things Applications

A Digital-Intensive Wakeup Timer based on an RC Frequency-Locked Loop for Internet-of-Things Applications

Zhou, Zhihao (TU Delft Electrical Engineering, Mathematics and Computer Science)

Sebastiano, Fabio (mentor)
Ding, Ming (mentor)
Liu, Yao-Hong (graduation committee)

Delft University of Technology

2017-11-27

This thesis presents an ultra-low power wakeup timer locked to an RC time constant that can meet the stringent power requirements of the nodes for Internet-of-Things (IoT) applications. The wakeup timer, fabricated in a 40-nm CMOS process, employs a bang-bang digital-intensive frequency-locked loop (DFLL). A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a chopped dynamic comparator and a digital loop filter, enabling an operation down to 0.65 V and a small area of 0.07 mm2. The digital-intensive design consumes 181 nW with an output frequency of 417 kHz. Thus, it achieves the best power efficiency (0.43 pJ/Cycle) at the lowest supply voltage (0.7 V nominal) over the state-of-the-art for ultra-low-power timers, while keeping on-par long-term stability (Allan deviation floor below 10 ppm) and temperature stability (106 ppm/°C).

oscillator
IoT
wakeup timer
FLL

http://resolver.tudelft.nl/uuid:5815b38c-668e-4f3a-8bb7-e01ef76d7e3f

2018-12-01

Student theses

master thesis

© 2017 Zhihao Zhou