Print Email Facebook Twitter An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop Title An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop Author Chen, Peng (University College Dublin) Huang, Xiongchuan (Broadcom) Chen, Y. (TU Delft Electronics) Wu, Lianbo (ETH Zürich) Staszewski, R.B. (University College Dublin) Date 2018 Abstract To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ΔΣ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement. Subject buit-in selft-test (BIST)CalibrationCharge pumpsClocksDelaysDigital-to-time converter (DTC)first-order delta-sigma modulatorLinearitynoise shapingPLLself calibrationSystem-on-chiptime-to-digital converter (TDC) To reference this document use: http://resolver.tudelft.nl/uuid:5909bdfd-96d0-458a-af10-dcebf257e94b DOI https://doi.org/10.1109/TCSI.2018.2857999 ISSN 1549-8328 Source IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 65 (11), 3734-3744 Part of collection Institutional Repository Document type journal article Rights © 2018 Peng Chen, Xiongchuan Huang, Y. Chen, Lianbo Wu, R.B. Staszewski Files PDF 46622288_08436438.pdf 2.63 MB Close viewer /islandora/object/uuid:5909bdfd-96d0-458a-af10-dcebf257e94b/datastream/OBJ/view