Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis

As we are moving toward nanometre technology, the variability in the circuit parameters and operating environment (Process, Voltage and Temperature (PVT)) are increasing, causing uncertainty in the circuit performance. Statistical Static Timing Analysis (SSTA) is a category of methodologies to analyse the variations in delay due to PVT variations. This thesis work is a part of the MODERN project, which is involved in developing a new SSTA methodology. In this thesis, the variation of the delay in 45nm standard cells is analysed. In industry practice, the Monte Carlo method is often used to estimate the statistical moments. This method needs a large number of simulation iterations and these simulations are parameter distribution dependent. A fast statistical moment estimation method is proposed in this work. The proposed methodology is at least 100 x faster than the Monte Carlo method and simulations are independent of the parameter distribution. In the SSTA methodology of the MODERN project, the signal waveforms with their variations are preserved at each pin of the standard cell. The concept of a "set of waveforms" as a representation of a variable electrical signal is also developed in this thesis work. Possible methods to represent the set of waveforms and their integration with the timing analysis methodology are analysed. The pseudo circuit based representation turns out to be the most compact model. A methodology for the analysis of the accuracy and efficiency of the pseudo circuit model is proposed.

Subject

STA
SSTA
digital circuit
timing analysis
EDA
PVT
variation
Monte Carlo
45nm
methodology
simulation
MODERN

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Student theses

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master thesis

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