Print Email Facebook Twitter Compiler Strategies for Transport Triggered Architectures Title Compiler Strategies for Transport Triggered Architectures Author Janssen, J. Contributor Van de Goor, A.J. (promotor) Corporaal, H. (promotor) Faculty Information Systems and Technology Date 2001-09-17 Abstract Compiler technology plays an important role to enhance the performance of modern microprocessors. In this thesis, compiler techniques and strategies are described to enhance the performance of microprocessors based on the Transport Triggered Architecture. The interaction between two important phases in a compiler, instruction scheduling and register assignment is described. Analysis and experiments show that considering these two phases separately has major performance drawbacks. A new technique, integrated assignment, is introduced which integrates instruction scheduling and register assignment in a single phase. The presented experiments clearly demonstrate the benefit of this approach for various scheduling scopes. Another topic addressed in this thesis is the complexity of the register file. It is shown that a partitioning of the register file results in a reduced chip area, a smaller access time and lower power dissipation at the expense of only a very small cycle count increase. This solves the register file problem within future high-end microprocessors. Subject compilersinstruction schedulingregister assignment To reference this document use: http://resolver.tudelft.nl/uuid:6f4aaf07-47b6-485c-b2b9-4a02df71a7a5 Publisher Delft University Press ISBN 90-407-2209-9 Part of collection Institutional Repository Document type doctoral thesis Rights (c) 2001 J. Janssen Files PDF its_janssen_20010917.pdf 1.59 MB Close viewer /islandora/object/uuid:6f4aaf07-47b6-485c-b2b9-4a02df71a7a5/datastream/OBJ/view