Fault tolerance on the ?-VEX processor

Fault tolerance on the ?-VEX processor

Meun, K.

Wong, J.S.S.M. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

2015-11-23

Increased technology scaling not only resulted in a performance increase of the microprocessor, but also led to increasing device vulnerability to external disturbances. Scaling accelerates ageing induced failures of CMOS devices and the average lifetime of electronic devices diminishes. This thesis describes the design and implementation of a fault-tolerant method to the p-VEX processor capabilities in order to counter these effects. The p-VEX processor is a Very Long Instruction Word (VLIW) softcore processor with the capabilities to reconfigure the issue width dynamic during run-time. Furthermore, this thesis discusses the implementation of not traditional Triple Modular Redundancy (TMR) with the existing issue width of the core by reconfiguring to a four times 2-issue width. In this method. an important section in the code can be marked and executed in three lock-stepped 2-issue width pipelines. Majority voters are implemented between these three pipelines to vote the results from the executions. At the cost of a 6% increase in resources and without great structural changes, a new capability is added which allows the p-VEX processor to continue running even when it suffers from single-event upsets (SEUs). With the implemented design the amount of errors is monitored using majority voters. Moreover, it is possible to initiate a switch from 2-issue width to the unused issue-width without introducing delay. The design is compared with the original p-VEX processor and tested by injecting errors in several units during executing. During these fault injections the TMR was able to correct these errors and complete the program without adding extra cycles.

VLIW
?-VEX
fault tolerant
tmr

http://resolver.tudelft.nl/uuid:744a8044-94ea-48b7-b6db-e17f0d3a417d

Student theses

master thesis

(c) 2015 Meun, K.