Print Email Facebook Twitter System Level Support for Dynamic Partial Reconfiguration Title System Level Support for Dynamic Partial Reconfiguration Author Nandy, A. Contributor Sourdis, I. (mentor) Gaydadjiev, G.N. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Computer Engineering Programme Computer Engineering Date 2011-09-28 Abstract In this thesis a generic approach for integrating a dynamically reconfigurable device into a general purpose system interconnected with a high-speed interconnect, is described. The system dynamically installs and executes hardware instances implementing functions to accelerate parts of a particular workload. The hardware descriptions of the functions (bitstreams) are inserted into an united executable running on the host. This is achieved through an extension to the GCC compiler which in addition inserts system-calls to the device driver controlling the reconfigurable device. Thereafter, the general purpose host-processor manages the hardware reconfiguration and execution through a Linux device driver. The device has direct access to the main memory (DMA) operating on virtual addresses; it further supports memory mapped IO for data and control, and is able to interrupt the host for synchronization. The above system is implemented on a general purpose AMD Opteron-244, and 1 GB of DDR memory providing a HyperTransport bus to connect a Xilinx Virtex4-100 FPGA. Moreover to facilitate automatic generation of hardware, an open source C to VHDL compiler is used. Finally, our proposal is evaluated using a secure audio processing application. This is done through acceleration of the audio processing kernel in hardware and subsequently an AES encryption function is configured via dynamic partial reconfiguration. Experimental results with up to 2GB of data show that our solution is up to 12 times faster than pure software execution. Subject FPGAhypertransportROCCC To reference this document use: http://resolver.tudelft.nl/uuid:7e5ccc35-774e-41d6-b12a-a502b1960256 Part of collection Student theses Document type master thesis Rights (c) 2011 Nandy, A. Files PDF ThesisMscAbhijitNandy.pdf 5.29 MB Close viewer /islandora/object/uuid:7e5ccc35-774e-41d6-b12a-a502b1960256/datastream/OBJ/view