Print Email Facebook Twitter Area Minimization of DTB Multiplexer Title Area Minimization of DTB Multiplexer: A Chip Component with High Wire Density and Congestion Author Cangga Putra, Reynaldi (TU Delft Electrical Engineering, Mathematics and Computer Science) Contributor van Leuken, Rene (mentor) Wielage, Paul (graduation committee) Degree granting institution Delft University of Technology Programme Computer Engineering Project NXP BAP3 Chip Date 2019-03-29 Abstract DTB Multiplexer is a component within an NXP chip called the BAP3. This component provides a testing functionality for the chip. This component is purely combinational, and requires no clock, however this makes the component wiring-costly. This high wiring requirement leads to the area constraint imposed by the wiring demand rather than cell area, and this also leads to the DTB multiplexer reducing the placement area available for other modules. In this thesis, the wiring area is going to be estimated as the amount of congestion, which would cause detour in the design which results in extra wiring. In this thesis, DTB multiplexer is placed by external method instead of using the place and route tools usually used by the design team. Instead, the placement is done on MATLAB which is later ported to the place and route tools using script. The placement algorithm implemented in MATLAB is primarily based on two algorithm, Dplace for initial preplacement, which in turn utilizes diffusion preplacement algorithm, and modified C-ECOP for the congestion reduction. More detailed congestion estimation done by using an additional routing estimation algorithm which is based on One-Steiner routing algorithm. The result indicates that the modified C-ECOP can be used to reduce congestion, thus wiring area when paired with a good initial placement algorithm, but the initial placement algorithm and detailed congestion estimation algorithm with one-steiner could be further improved, and further work is needed to integrate the result with commercial Subject placementwiring areacongestionoverflowquadratic placementwirelength To reference this document use: http://resolver.tudelft.nl/uuid:836ecbef-6bad-48a4-9326-50ab19e5c33f Part of collection Student theses Document type master thesis Rights © 2019 Reynaldi Cangga Putra Files PDF revised_report_reynaldi_c ... 518888.pdf 2.5 MB Close viewer /islandora/object/uuid:836ecbef-6bad-48a4-9326-50ab19e5c33f/datastream/OBJ/view