Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits

Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits

Zheng, X.Y.

Berkelaar, M. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

2012-08-29

Static Timing Analysis (STA) is one approach to verify the timing of a digital circuit. The currently used Gate Level Model (GLM) has limitations on performing STA for circuits when taking process variations into consideration. The transistor level model is developed taking the statistical factors into account. This thesis presents an implementation of the simplified transistor model in Verilog-AMS such that the model can be installed as a compiled model in existing commercial circuit simulators, such as Spectre. A direct comparison between the proposed transistor model and the sophisticated Berkeley Short-channel IGFET Model (BSIM) is presented. Furthermore, the transistor model is extended with process variations awareness for statistical timing analysis. The polynomial curve fitting scheme is proposed in this thesis to improve the model accuracy. The evaluation results indicate that the proposed method has approximately 70% improvement in terms of estimating one of the components i.e., drainsource current Ids for the statistical transistor model.

Static Timing Analysis
Verilog-AMS
transistor level model
spectre
polynomial curve fitting
statistical timing analysis

http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60

Student theses

master thesis

(c) 2012 Zheng, X.Y.