90 nm VLSI Design of an 8-bits Microcontroller

90 nm VLSI Design of an 8-bits Microcontroller

Moar Gomez, J.

Van Leuken, T.G.R.M. (mentor)
Van der Veen, A.J. (mentor)
Serdijn, W.A. (mentor)

Electrical Engineering, Mathematics and Computer Science

2009-02-26

Integrated Circuit (IC) design complexity has increased radically since the first "hand-made" designs in the late 50s, with a few transistors. Nowadays, Very Large Scale Integration (VLSI) designs contains hundreds thousand, million or even billion transistors and not only the experience of the designer, but also Electronic Design Automation (EDA) tools and some methodology is needed. The purpose of this thesis is the design in 90nm UMC technology of an 8-bit microcontroller for its final manufacture using Modelsim, Design Compiler and SoC Encounter and following a standard cell design methodology. During the different steps of the VLSI flow (behavioural specification and verification, synthesis and layout generation), it will be shown how to deal with the design issues that arise: (DFT insertion, clock gating, clock\&reset tree generation, etc.). Starting from a tested FPGA implementation in VHDL based on the AVR ATmega103 microcontroller from ATMEL, the final result is an 8-bit microcontroller with the following features: 16k x 16 bits of Program Memory (PM), 8K bytes Data Memory (DM), 256 bytes parameter memory, 3 8bits I/O ports, UART, SPI, JTAG interface, additional PM programming capability (apart from the JTAG) and Wishbone interface including an USB 1.1 slave and another slave to implement and test a simple scan chain prototype. In addition the clock frequency can be increased up to 200 MHz.

vlsi
microcontroller
90nm
wishbone

http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc

TU Delft, Electrical Engineering, Mathematics, Computer Sci, Microelectronics

Student theses

master thesis

(c) 2009 J. Moar Gomez