Print Email Facebook Twitter Iterative Instruction Scheduling for a VLIW Processor Title Iterative Instruction Scheduling for a VLIW Processor Author Vahedi, M. Contributor Turjan, A. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics & Computer Engineering Programme CE Date 2013-02-26 Abstract Instruction scheduling aims to reorder instructions in such a way that it covers the delay between an instruction and its dependent successor(s). As a result, the length of schedules are shortened while the processor utilisation increases. This is accomplished by exploiting Instruction Level Parallelism (ILP). The rearrangements made by instruction scheduling plays an important role in achieving the peak performance of a processor, especially for the ones which do not support out-of-order execution. Optimal scheduling to minimise the number of cycles under an arbitrary pipeline constraints is an NP-complete problem. Hence, most schedulers rely on heuristics in order to arrange the instructions. Although these heuristics are widely used and frequently lead to a fairly good solution, there still might be another instruction order which is better. In this work we bring randomisation to the GNU Compiler Collection GCC) list scheduler to explore the area of possible orders beyond the heuristics. Our core approach involves swapping the priorities of instructions, which does not totally discard the scheduling heuristics. It starts exploring the search space from a fairly good solution obtained by these heuristics. Moreover, as a result of using randomisation in the scheduler, some other problems have been tackled, such as: which part of the search space to explore in a limited amount of time, getting an approximation of how much of the search space is explored, how to fill the delay slots more effiently, etc. We evaluated our algorithms in compilation of programs for a Very Long Instruction Word (VLIW) processor called Embedded Vector Processor (EVP) from ST-Ericsson. Since EVP is used as an embedded Digital Signal Processor (DSP) in mobile devices, it is crucial to have a simple architecture to save power. Which is why, EVP is a non-interlocked exposed pipeline and is highly dependent on the compiler to exploit ILP. Subject instruction schedulingcompilergccevpembedded vliw To reference this document use: http://resolver.tudelft.nl/uuid:8d4669d3-d4a0-46b0-a796-30b3b1a28b0d Embargo date 2016-02-01 Part of collection Student theses Document type master thesis Rights (c) 2013 Vahedi, M. Files PDF thesis.mvahedi-itertive-s ... essors.pdf 1.38 MB Close viewer /islandora/object/uuid:8d4669d3-d4a0-46b0-a796-30b3b1a28b0d/datastream/OBJ/view