Scalable Multigigabit Pattern Matching for Packet Inspection

Scalable Multigigabit Pattern Matching for Packet Inspection

Sourdis, I.
Pnevmatikatos, D.N.
Vassiliadis, S.

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

2007-05-28

In this paper, we consider hardware-based scanning and analyzing packets payload in order to detect hazardous contents.We present two pattern matching techniques to compare incoming packets against intrusion detection search patterns. The first approach, decoded partial CAM (DpCAM), predecodes incoming characters, aligns the decoded data, and performs logical AND on them to produce the match signal for each pattern. The second approach, perfect hashing memory (PHmem), uses perfect hashing to determine a unique memory location that contains the search pattern and a comparison between incoming data and memory output to determine the match. Both techniques are well suited for reconfigurable logic and match about 2200 intrusion detection patterns using a single Virtex2 field-programmable gate-array device. We show that DpCAM achieves a throughput between 2 and 8 Gb/s requiring 0.58–2.57 logic cells per search character. On the other hand, PHmem designs can support 2–5.7 Gb/s using a few tens of block RAMs (630–1404 kb) and only 0.28–0.65 logic cells per character. We evaluate both approaches in terms of performance and area cost and analyze their efficiency, scalability, and tradeoffs. Finally, we show that our designs achieve at least 30% higher efficiency compared to previous work, measured in throughput per area required per search character

Packet inspection
pattern matching
perfect hashing
reconfigurable computing

http://resolver.tudelft.nl/uuid:8f81f21e-6c28-4829-a0db-0530cfd5ae57

IEEE

1063-8210

IEEE Transactions on very large integration (VLSI) systems, 16 (2), 2008

Institutional Repository

journal article

(c) 2007 IEEE