Efficient inter-thread communication on the reconfigurable ρ-VEX

Efficient inter-thread communication on the reconfigurable ρ-VEX

Dirks, Jacko (TU Delft Electrical Engineering, Mathematics and Computer Science)

Wong, Stephan (mentor)
Al-Ars, Zaid (graduation committee)
Spaan, Matthijs (graduation committee)

Delft University of Technology

2018-06-25

This thesis documents the implementation of atomic instructions for the ρ-VEX (reconfigurable VEX). These instructions enable threads to communicate enabling efficient multithreading. Furthermore, we investigate the possibility to use inter-thread communication to improve performance of static ρ-VEX configurations without significantly increasing the area. Benchmark results show that the ρ-VEX can perform up to 1.33 times better because of the addition
of atomic instructions.
Moreover, the combination of reconfigurability and inter-thread communication is investigated to determine the possible performance improvement resulting from this combination. A theoretical model is created which predicts that a runtime reconfigurable ρ-VEX is able to outperform any static ρ-VEX setup. Given ideal circumstances, the runtime reconfigurable ρ-VEX can be 20% to
100% faster than any static ρ-VEX.
In addition, this thesis documents the implementation of a bridge which intertwines the ρ-VEX with ARM’s ZYNQ system, a single chip containing an ARM processor and a Xilinx field-programmable gate array (FPGA). This bridge gives the ρ-VEX access to a 512 MiB memory on the Basys PYNQ.

rVEX
multithreading
Performance

http://resolver.tudelft.nl/uuid:9287bcea-f455-42fc-9efe-9417dbcbd4ad

Student theses

master thesis

© 2018 Jacko Dirks