A 32 x 32 Spiking Neural Network System On Chip

Title

A 32 x 32 Spiking Neural Network System On Chip

 Author

Stienstra, Ester (TU Delft Electrical Engineering, Mathematics and Computer Science; TU Delft Microelectronics)

Contributor

van Leuken, Rene (mentor)

Degree granting institution

Delft University of Technology

 Programme

Electrical Engineering

 Date

2017-08-29

 Abstract

In this thesis a prototyping system on chip of a 32 x 32 spiking neural network is presented. This network has been designed in UMC 65. In order to determine which neuron model to use three different analog CMOS neuron models are studied. One of these models is used in the network. The network consists of arrays of synapses and neurons, 32 synapses for each neuron.
In order to be able to control all the synaptic inputs and read all the neural outputs, logic is presented that minimizes the number of pads needed, while maintaining controllability and keeping all the important information in the neural signal.
Simulations are performed to determine the influence of several
behaviors of the neuron and the synapse on the output of the network.
Also a floorplan and place and route design for the chip are presented.

 To reference this document use:

http://resolver.tudelft.nl/uuid:94d5f6b7-3d06-4b7a-9f39-0b346083386e

 Part of collection

Student theses

 Document type

master thesis

 Rights

© 2017 Ester Stienstra
Files
PDF Thesis_Ester_Stienstra.pdf 11.76 MB
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