Streaming FPGA Based Multiprocessor Architecture for Low latency Medical Image Processing

Streaming FPGA Based Multiprocessor Architecture for Low latency Medical Image Processing

Heij, R.W.

Al-Ars, Z. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

Computer Engineering

CE-MS-2016-15

2016-12-02

In this work a fast and efficient implementation of a Field Programmable Gate Array (FPGA) based, fixed hardware, streaming multiprocessor architecture for low latency medical image processing is introduced. The design of this computation fabric is based on the ρ-VEX Very Long Instruction Word (VLIW) softcore processor and is in influenced by architectures of modern Graphics Processing Unit (GPU) implementations. The computation fabric is capable of exploiting several types of parallelism, including pipelining, Instruction-level Parallelism (ILP) and Data-level parallelism (DLP). The multiprocessor in the fabric is implemented by a chain of ρ-VEX processors that function as a processor pipeline. A memory architecture to support the high throughput of this processor pipeline has been created, making the computation fabric capable of stream processing. The basic building blocks of this memory architecture are single cycle accessible, dual port scratchpad memories. A total of 16 instances of the computation fabric are implemented on a Virtex-7 FPGA, creating an array of multiprocessors that is capable of processing 43.52 images per second when running a typical medical image processing algorithm workload on an operating frequency of 193 MHz. This makes the implementation suitable for real-time medical image processing. The processor pipeline depth of the computation fabric is generic, and can be changed according to the requirements posed by the algorithm workload. This makes the architecture flexible and general enough to handle changes and updates to the algorithm workload.

FPGA
r-VEX
Streaming
Processor
Medical image processing

http://resolver.tudelft.nl/uuid:97e95a0e-a9d1-4ecd-b4c2-717217ab8a0e

2017-12-01

Student theses

master thesis

(c) 2016 Heij, R.W.