Print Email Facebook Twitter A Highly Concurrent, Memory-Efficient AER Architecture for Neuro-Synaptic Spike Routing Title A Highly Concurrent, Memory-Efficient AER Architecture for Neuro-Synaptic Spike Routing Author Coenen, Joris (TU Delft Electrical Engineering, Mathematics and Computer Science) Contributor van Leuken, T.G.R.M. (mentor) Al-Ars, Z. (graduation committee) Kumar, S.S. (graduation committee) Zjajo, Amir (graduation committee) Degree granting institution Delft University of Technology Programme Electrical Engineering | Circuits and Systems Date 2019-04-17 Abstract One of the challenges of neuromorphic computing is efficiently routing spikes from neurons to their connected synapses. The aim of this thesis is to design a spike-routing architecture for flexible connections on single-chip neuromorphic systems. A model for estimating area, power consumption, memory, spike latency and link utilisation for neuromorphic spike-routing architecture is described. This model leads to the proposal for a new spike-routing architecture with a hybrid addressing scheme and a novel synaptic encoding scheme. The proposed architecture is implemented in a SystemC simulation tool with a supporting tool for encoding arbitrary SNN topologies for the synapse encoding scheme. Running the simulations with synthetic benchmarks and a handwriting recognition SNN shows that the proposed architecture is memory-efficient and provides low latency spike-routing with high synaptic activation concurrency. Subject neuromorphic systemsaerspike-routing To reference this document use: http://resolver.tudelft.nl/uuid:9a2013f0-7e94-4068-b6b9-c61e366dfb0f Embargo date 2020-04-18 Part of collection Student theses Document type master thesis Rights © 2019 Joris Coenen Files PDF MSc_thesis_Joris_Coenen_c ... rected.pdf 2.88 MB Close viewer /islandora/object/uuid:9a2013f0-7e94-4068-b6b9-c61e366dfb0f/datastream/OBJ/view