ρ-VEX ASIC

ρ-VEX ASIC: The Design of an ASIC for a Dynamically Reconfigurable VLIW Processor with 24-port Register File

van Bremen, Lennart (TU Delft Electrical Engineering, Mathematics and Computer Science)

Wong, Stephan (mentor)
van Leuken, Rene (graduation committee)
Al-Ars, Zaid (graduation committee)

Delft University of Technology

2017-08-30

The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.
A fully automatic scripted flow is described, constructing an optimized, error-free ASIC. The design area is limited to 3.5 um², to allow it to be manufactured with the cheapest 65 nm prototyping run available at IMEC. In order to achieve this small design area, a new 24-port register file design has to be devised. In its current state, it is implemented using standard logic cells. Clever optimizations involving cell padding and minimum overhead power routing are necessary to reduce a total routing overcongestion from 7% to zero.
This implementation is expected achieve a clock speed of 141 MHz, only limited by the ρ-VEX reconfiguration logic. By lowering the frequency to 100 MHz, the energy dissipation is reduced by 96%, to a total of 367 uW/MHz. This is comparable to similar VLIW designs. Using LVDS communication clocked at four times the core frequency, a data bandwidth of 4 Gbit/s is achieved using only 26 external pins. This allows the main data and instruction memory to reside off-chip.
To ensure a correct design, it is verified using DRC, LVS, and ERC. For improved reliability, IR-drop is kept within 1% of the core voltage, using minimal power routing. Furthermore, the effect of electromigration is kept extremely low such that the mean time to failure on nets is 90 years.
The scripted flow will aid in prototyping, allowing accurate estimates to be calculated in a mere 7% of the original time. Proposals for a future design are expected to reduce the register file area and power dissipation by more than 40%. By improving the pipeline and shortening the critical path, a two to four fold improvement in clock speed can be expected, without adversely affecting power dissipation.

r-VEX
VLIW
ASIC
LVDS
Register file
UMC
65nm

http://resolver.tudelft.nl/uuid:a007db49-10c7-4ae6-ac84-1cf0dfdb818d

Student theses

master thesis

© 2017 Lennart van Bremen