Print Email Facebook Twitter A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV ppSupply Ripple Title A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV ppSupply Ripple Author Chen, Y. (TU Delft Electronics) Gong, J. (TU Delft QCD/Sebastiano Lab) Staszewski, R.B. (TU Delft Electronics; University College Dublin) Babaie, M. (TU Delft Electronics) Date 2022 Abstract In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on- chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <-55-dBc fractional spur, and <-54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mVpp at 50-MHz reference divided by 3, 6, or 12. Subject CalibrationCurrent digital-to-analog converter (DAC)dc-dc converterDelaysdigitally intensive phase-locked loop (DPLL)inductor-capacitor (LC) oscillatorJittermultimodulus divider (MMDIV)OscillatorsPhase locked loopsresampleripple pattern estimation and cancellationripple replication and cancellationSensitivityslope generator (SG)successive approximation register (SAR) analog-to-digital converter (ADC)supply pushingsupply ripple.Voltage To reference this document use: http://resolver.tudelft.nl/uuid:a3c2878c-c4df-4865-8fb5-9351d0929478 DOI https://doi.org/10.1109/JSSC.2021.3123386 ISSN 0018-9200 Source IEEE Journal of Solid State Circuits, 57 (6), 1749-1764 Part of collection Institutional Repository Document type journal article Rights © 2022 Y. Chen, J. Gong, R.B. Staszewski, M. Babaie Files PDF A_Fractional_N_Digitally_ ... Ripple.pdf 5.57 MB Close viewer /islandora/object/uuid:a3c2878c-c4df-4865-8fb5-9351d0929478/datastream/OBJ/view