ADPLL Design for WiMAX

ADPLL Design for WiMAX

Jiang, W.

Staszewski, R.B. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

Microelectronics

2011-09-22

The frequency synthesizer, which functions as a local oscillator, is a critical block in the transceiver. It needs to meet very stringent specifications and consume as less power as possible. Design of a traditional charge-pump PLL as the frequency synthesizer in the advanced CMOS technologies in the transceiver of advanced communication systems proves to be not an easy work and is becoming difficult due to the supply shrink. The ADPLL system, which defines every essential block with digital interface, proves to be an excellent alternative. This thesis deals with the system level design of ADPLL for the WiMAX standard. The architecture of the ADPLL is presented, with the functional illustration for every building block, like DCO and TDC. The ADPLL system is modeled and described in Cadence using Verilog-AMS/Verilog. The performance of the system is analyzed in s-domain. Some advanced algorithms have been applied to the ADPLL system. The spur mechanism in the near-integer N cases is proposed and verified. The phase rotation algorithm and the FREF dithering algorithm have been adopted to effectively suppress these spurs. The top level issues of ADPLL are tackled, with emphasis on the test plan and the operation modes of the system. The behavior level simulation results of the system are presented and the performance summary is given. The transistor level design of a basic DPA is presented. The layout for the important blocks is done and the practical concerns of the DPA design are discussed. The post-extraction simulation results are shown.

ADPLL
WiMAX
Frequency synthesizer
CMOS

http://resolver.tudelft.nl/uuid:abe493a5-49d3-4822-8186-9ed1b15d3eaf

2011-09-22

Student theses

master thesis

(c) 2011 Jiang, W.