Open-source IP cores for space

Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era

Di Mascio, S. (TU Delft Space Systems Egineering)
Menicucci, A. (TU Delft Space Systems Egineering)
Gill, E.K.A. (TU Delft Space Engineering)
Furano, Gianluca (European Space Agency (ESA))
Monteleone, Claudio (European Space Agency (ESA))

Space Engineering

2021

This paper discusses principles and techniques to evaluate processors for dependable computing in space applications. The focus is on soft errors, which dominate the failure rate of processors in space. Error, failure and propagation models from literature are selected and employed to estimate the failure rate due to soft errors in typical processor designs. A similar approach can be followed for applications with different radiation environments (e.g. automotive, servers, experimental instrumentation exposed to radiation on ground), by adapting the error models. This detailed white-box analysis is possible only for open-source Intellectual Property (IP) cores and in this work it will be applied to several open-source IP cores based on the RISC-V Instruction Set Architecture (ISA). For these case studies, several types of redundancy described in literature for space processors will be evaluated in terms of their cost-effectiveness and expected final in-orbit behavior. This work provides a comprehensive framework to assess efficacy and cost-effectiveness of redundancy, instead of listing and categorizing the techniques described in literature without assessing their relevance to state-of-the-art designs in space applications.

Fault tolerance
Processors
Space

http://resolver.tudelft.nl/uuid:b564ddd4-b1f2-4628-af93-7983c32dd0ea

https://doi.org/10.1016/j.cosrev.2020.100349

1574-0137

Computer Science Review, 39

Institutional Repository

review

© 2021 S. Di Mascio, A. Menicucci, E.K.A. Gill, Gianluca Furano, Claudio Monteleone