The work presented in this thesis was performed in the context of the European Sixth Framework Program FP6 project “Disposable Dot Field Effect Transistor for High Speed Si Integrated Circuits”, referred to as the D-DotFET project. The project had the goal of realizing strain-enhanced mobility in CMOS transistors by transferring strain from a self-assembled germanium dot to the channel of a transistor fabricated above the dot. The initial idea was to dispose of the Ge dot underneath the channel after the gate processing so that the gate-stack would also serve to stabilize the channel-bridge and maintain the strain induced in the channel silicon by the Ge dot. The advantage of using a SiGe dot as a strain source is its scalability to as low as 10 nm gate dimensions, which is not obvious for currently used methods for imparting strain on the Si channel. Furthermore, the D-DotFET structure offers advantages for the electrostatic and electrothermal behavior of MOS devices. For example, SOI devices with fully-depleted channel are a solution for short-channel effects but the insulating oxide beneath the device introduces a thermal management issue. This problem is solved in Silicon-on-Nothing (SON) devices because the insulating region is then only found under the gate with the source and drain regions still being anchored to the thermally conductive bulk silicon. The D-DotFET resembles the SON transistor but with the added advantage of strain-enhanced device gain and speed. In that way the D-DotFET combines four potential improvements: strain enhanced performance, scalability to future ~ 10 nm generations, suppression of short-channel effects, and good heat dissipation. Research was done in several areas to assure that the stringent requirements on uniformity, reproducibility and reliability could potentially be met to transfer the D-DotFET concept to advanced CMOS. The growing of silicon germanium (SiGe) dots with the necessarily high Ge content was first developed, and uniformity and reproducibility were brought to a high level of perfection. The strain of both bare and overgrown dots was extensively analyzed both experimentally and theoretically. Then, the strain that could be transferred to the channel of a MOSFET was evaluated in terms of mobility enhancement via device simulations, and lastly, the actual integration of dots was demonstrated in a low-complexity n-MOSFET research process that was specially tailored to this application, which is the topic of this thesis. The Dimes cleanrooms were not equipped to set up a state-of-the-art CMOS process to investigate the D-DotFET concept. However, the available expertise and equipment was suitable for running a more advanced process, where excimer laser annealing could be implemented to replace the standard rapid thermal annealing and a metal gate could replace the standard polysilicon gate. Furthermore, the patterning of ~ 100 nm gate features was performed by e-beam lithography by the project partner Forschungszentrum Jülich. To avoid as many nanoscale lithography steps as possible, geometry with large source-drain contacting areas was devised so that only one step, the ~ 100 nm gate definition itself, needed to be patterned by e-beam. Additionally, since the goal was in first instance to verify the strain-enhanced gain induced by the dot, it was decided to significantly simplify the transistor processing by retaining the dot throughout. A “DotFET” rather than a “D-DotFET” was therefore fabricated. This meant that only low-temperature processing steps could be performed after the dot formation, in order to avoid intermixing of Si and Ge and consequent strain relaxation. This was realized in a dedicated n-MOSFET process where the temperature was kept below 400?C after epitaxy by using low-temperature gate dielectrics and a metal gate self-aligned to implanted and laser annealed source/drain regions. The SiGe dots used for the DotFET fabrication were grown in a self-assembling Stranski-Krastanow mode that allows single-crystalline dots of SiGe to grow in three-dimensions on predefined seedholes. Under appropriate conditions this growth is defect free and can easily be scaled down. The 3D growth of the SiGe allows a higher Ge content inside the dot before the onset of crystal dislocations as compared to the growth of 2D SiGe layers of similar thickness. The smaller the SiGe dots the higher the Ge content that can be maintained without defect formation and consequently a higher strain can be exerted on any Si layer grown over the dot. For the devices described in this thesis, the dots were grown by MBE on a regular seedhole pattern of submicron periodicity etched into the Si. The growth was investigated in detail to determine the optimum growth conditions and seedhole-patterns for achieving a dot-size and strain level suitable for constructing a MOSFET over the center of the dot structure where the biaxial tensile strain could be exploited for channel mobility enhancement. For a uniform and reproducible SiGe dot growth, excellent results were achieved by a location-controlled growth method where large, regular arrays of seedholes are patterned on an otherwise flat Si substrate. In the present work, both i-line optical lithography and e-beam lithography (EBL) were used to pattern such holes in (100) Si wafers. In the case of e-beam lithography a very good control of the seedhole positions and size is obtained and the resulting dots are extremely regular. The present DotFET fabrication required a dot size that could accommodate a gate of length ~ 100 nm. For this purpose the most suitable seedhole arrays were the ones with a periodicity of 800 nm that rendered a maximum dot diameter in the range of 230 nm. EBL patterning of this configuration was used for the device fabrication, while analysis of the dot properties was also performed on samples processed with optical lithography. The growing of the dots on the seedhole pattern starts with the deposition of a Si buffer layer which smoothes the surface. The dots are then grown at 720?C from a pure Ge source In Chapter 2, a simple, low-temperature process flow for achieving good quality ultrashallow n+p junction diodes has been demonstrated for 5 keV As+ implants activated by excimer laser annealing. Much research has recently been done using ELA techniques due to the extremely short annealing times that potentially eliminate transient enhanced diffusion effects, reach high levels of dopant activation and give abrupt junctions. Compared to conventional rapid thermal anneal procedures ELA offers the advantage of a good control of the junction depth, where a reduction of the vertical implantation range can serve as a direct means of also decreasing the junction depth. The laser processing research performed at Dimes in the past, rather than being aimed at the fabrication of source and drain regions for CMOS, has been motivated by the need to have access to good quality diodes in integration situations where only very low temperatures are permitted, such as in silicon-on-glass processing. With respect to the bulk laterally-uniform part of the diode away from the perimeter, it is important that the Si-surface to be implanted is smooth and native-oxide free before implantation. The implant needs to be so shallow that the melt region encompasses the whole implanted region but deep enough to avoid laser-induced-surface-structuring effects on the Si surface from affecting the underlying metallurgic junction region. Tilted implants can reduce the final junction depth of the 5 keV implants to below 20 nm. With respect to the perimeter of the diode, the key to achieving diodes of good quality is the termination of the metallurgic junction at an oxide-to-silicon interface that is of good quality. In the presented experiments this is achieved by using a thin layer of thermal oxide to cover the Si under a thicker low-temperature isolation layer. The oxide at the interface is a 30-nm-thin layer of thermal oxide, which is still sufficiently thick to avoid excessive widening of the contact window during the dip-etch used to remove native oxide before metallization. After the growth of the isolation oxide, all processing steps are performed at temperatures below 400ºC. A reflective mask of Al is applied to localize the laser melting of the silicon to the desired diode region and to protect the perimeter. The tilted implants also increase the overlap of the oxide isolation with the diode perimeter, making the process more robust which in turn reduces perimeter leakage. The completeness of the laser melt at the perimeter depends on the thermal conductivity of the surroundings. Less melting of the perimeter with respect to the bulk is identified by TEM analysis in diodes processed in Dimes and this may be a source of extra perimeter leakage that needs to be taken into account when designing a specific process flow and diode structure. The best results are achieved here with an implant of 2x1015 cm-2 at tilt of 30?. For diodes with an area of 80 ?m2 this gives an ideality factor of 1.04 and reverse leakage at 2 V in 10-5 A/cm2 range. The low-temperature processing needed for the DotFET transistor puts heavy demands on the processing temperature of the gate dielectric which conventionally is a high-quality thermal oxide grown at temperatures above 850?C. In Chapter 3 a study is presented of a number of dielectric layer-stacks formed at temperatures below 400?C that could potentially be used as DotFET gate material. MIS capacitors were fabricated with different gate- dielectric layer stacks and electrically characterized, and a comparison was made to capacitors with a SiO2 interface layer thermally-grown at ? 700?C. It was chosen to investigate atomic-layer deposited Al2O3 layers because this technique gives an excellent uniformity, conformality, precise control of the thickness of the films, and it is possible to deposit high-quality layers at low temperature. Cycles of TMA and water were applied in order to deposit the Al2O3 layers at a temperature of 300?C. The SiOxNy films with a low concentration of N were grown by inductively coupled plasma at a temperature of 250?C. The results of capacitance-voltage and current-voltage measurements demonstrated that ALD Al2O3 and ICP SiOxNy exhibited a dielectric constant of 4 and 8, respectively. With ICP SiOxNy, capacitors were fabricated with low interface trap level density and low effective charge density, < 1011 cm-2eV-1 and <1011 cm-3eV-1, respectively, as well as low leakage current density (< 10-7 A/cm2). For pure Al2O3 layers the interface quality to Si was poor and in order to improve this situation, a high-quality interface layer was either grown or deposited between the alumina and Si substrate. Due to the simple, fast processing and good quality of the ICP SiOxNy dielectric at low temperature, the SiOxNy was finally chosen for the fabrication of the MOSFETs and DotFETs. The processing techniques for the fabrication of n+p diodes with ultrashallow junction annealed by excimer laser technique and capacitors using Al2O3 and SiOxNy gate dielectrics were combined to create a simple MISFET device presented in Chapter 4. The fabrication of n- and p-MISFET devices was demonstrated for processing temperatures below 400?C. Four important processing steps need to be performed in order to have good electrical device performance: (i) for a good quality growth of ICP-SiOxNy, the Si surface must be cleaned immediately before the growth, achieved with a HF dip-etch; (ii) a dip in BHF is performed immediately before source/drain implantation to remove the native oxide on the Si surface and achieve a uniform implantation of the low-energy ions; (iii) a RIE process with low RF power is used for oxide etching to open the source/drain contact windows in order to reduce damage to the implanted silicon surface; (iv) a HF dip-etch is used to remove native oxide before source/drain metallization and ensure a low-ohmic contacting. Both n- and p-MISFET devices show good performance, especially with respect to drain current driving capability. By increasing the laser energy, the sheet resistance of source/drain regions is reduced due to higher dopant activation. The source to drain resistance was also extracted from the measurements and an increase was observed when the channel length increases. Ultrashallow source/drain junctions were activated and the TEM images show junctions of 10-12 nm deep for 1000 mJ/cm2 laser energy. The overlapping of the laser spot was studied for 66% and 1% overlap. The drain current is higher for 66% overlap, again due to higher dopant activation but at a cost of some extra heating. In Chapter 5, the demonstration of high performance n-DotFET devices, successfully fabricated by adapting the n-MISFET process to the dot structure, is presented. Transistors with a minimum gate-length dimension of 50 nm using TiN/Al(1%Si) metal-gates were processed. A SiGe dot grown by MBE was used as stressor material. The best energies for excimer laser annealing of these structures were found to be between 850 mJ/cm2 and 900 mJ/cm2. E-beam lithography was used to define nanoscale gate dimensions in the central region of the dot and a 1-µm-wide gate finger is defined to contact this narrow gate. Thus a part of the current between the source and drain flows around the dot structure rather than through the silicon channel over the SiGe dot. Despite this effect, it is still possible to determine the influence of the strain on the drain current. The electrical characteristics show a drain current enhancement between 2% and 35%. The simulations show enhancements due to the strained Si layer of 20% - 22%. The small dimensions of the channel result in a large spread of measured characteristics, but nevertheless, the impact of the strain Si layer can be indentified. On a test sample the SiGe dot was removed using ammonium hydroxide, hydrogen peroxide and deionized water, which shows the possibility of fabricating a D-DotFET device in the future. Simulations of D-DotFETs and DotFETs fabricated on SOI substrates were done and the results show a reduction of self-heating for D-DotFET devices. Conclusions to the thesis are given in Chapter 6. The two most important results of this thesis are the demonstration of the applicability of (1) SiGe dots as stressor material and (2) full-melt high-power laser annealing as a technique for lowering the source/drain series resistance in a manner self-aligned to the gate.