An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs

Kuo, Feng-Wei (Taiwan Semiconductor Manufacturing Company (TSMC))
Babaie, M. (TU Delft Electronics)
Chen, Huan-Neng (Ron) (Taiwan Semiconductor Manufacturing Company (TSMC))
Cho, Lan-Chou (Taiwan Semiconductor Manufacturing Company (TSMC))
Jou, Chewn-Pu (Taiwan Semiconductor Manufacturing Company (TSMC))
Chen, Mark (Taiwan Semiconductor Manufacturing Company (TSMC))
Staszewski, R.B. (TU Delft Electronics)

2018

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <-107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits -157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <-91 dBc, while fractional spurs are <-55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm$^2$.

4G cellular
All-digital PLL (ADPLL)
digitally controlled oscillator (DCO)
long-term evolution (LTE)
spurs
time-to-digital converter (TDC)

http://resolver.tudelft.nl/uuid:bd6e56fd-2ea1-4a7f-8dbe-0154ce63742d

https://doi.org/10.1109/TCSI.2018.2855972

1549-8328

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 65 (11), 3756-3768

Institutional Repository

journal article

© 2018 Feng-Wei Kuo, M. Babaie, Huan-Neng (Ron) Chen, Lan-Chou Cho, Chewn-Pu Jou, Mark Chen, R.B. Staszewski