Determined-Safe Faults Identification

Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs

Augusto da Silva, F. (TU Delft Computer Engineering; Cadence Design Systems)
Bagbaba, Ahmet Cagri (Cadence Design Systems)
Sartoni, Sandro (Politecnico di Torino)
Cantoro, Riccardo (Politecnico di Torino)
Reorda, Matteo Sonza (Politecnico di Torino)
Hamdioui, S. (TU Delft Quantum & Computer Engineering)
Sauer, Christian (Cadence Design Systems)

Quantum & Computer Engineering

2020

The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.

ISO26262
Fault Injection
Safe Faults
Formal Methods
Simulation
Functional Safety
Verification

http://resolver.tudelft.nl/uuid:bdef7b9a-65df-4e1c-8dbd-a4f824d882f4

https://doi.org/10.1109/ETS48528.2020.9131568

IEEE

978-1-7281-4313-2

2020 IEEE European Test Symposium (ETS): Proceedings

ETS 2020, 2020-05-25 → 2020-05-29, Tallinn, Estonia

Accepted author manuscript

Institutional Repository

conference paper

© 2020 F. Augusto da Silva, Ahmet Cagri Bagbaba, Sandro Sartoni, Riccardo Cantoro, Matteo Sonza Reorda, S. Hamdioui, Christian Sauer