An Ultra-Low-Power ADPLL for BLE Applications

An Ultra-Low-Power ADPLL for BLE Applications

Wu, L.

Staszewski, R.B. (mentor)
He, X. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

ELCA

2014-11-20

In recent years, wireless personal area network (WPAN) applications have triggered the needs for low-cost and low-power PLLs which also provide good performance. All-digital phased-locked loops (ADPLLs) are preferred over their analog counterparts in nanoscale CMOS technology due to their flexibility, configurability, small area and easy portability. However, fractional spurs and insufficiently low power dissipation are main problems related to conventional TDC-based structures. In this work, a sub-half mW 2.2 GHz - 3 GHz fractional-N ADPLL is presented for Bluetooth Low Energy (BLE) applications. Coarse-fine DTC based phase predictor with dynamic element matching (DEM) ability and clock gated phase error freezer are proposed to reduce the power while maintaining good phase noise and fractional spur performance. This prototype ADPLL was taped out on Sep. 11th 2014 in GlobalFoundries 40 nm Low Power (40 nm-LP) technology. Based on post-layout simulations and modelling, it is expected to consume less than 450 ?W with integrated rms jitter of 1.5 ps for the close integer channel and 800 fs for the rest of channels, leading to a potential state-of-art FoM below -240 dB. Design of the full ADPLL in terms of system level analysis, digital logic, mixed-signal and RF design is presented in the thesis.

frequency synthesizer
ADPLL
ultra-low-power
DTC

http://resolver.tudelft.nl/uuid:c2897087-1a85-4cbe-918b-12b0c0837792

2016-02-20

Student theses

master thesis

(c) 2014 Wu, L.