A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 μV Offset

A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 μV Offset

Chae, Y. (Yonsei University)
Souri, K. (TU Delft Electronic Instrumentation)
Makinwa, K.A.A. (TU Delft Electronic Instrumentation)

2013

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time
of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm² chip was fabricated in a standard 0.16 μm CMOS process.

A/D conversion
and dynamic error correction techniques
battery-powered sensors
delta-sigma ADC
incremental ADC
inverter-based integrator
low power circuits
SAR ADC
zoom ADC

http://resolver.tudelft.nl/uuid:c7f8a139-278e-4ec8-b931-bb1fd671ff52

https://doi.org/10.1109/JSSC.2013.2278737

0018-9200

IEEE Journal of Solid State Circuits, 48 (12), 3019-3027

Accepted Author Manuscript

Institutional Repository

journal article

© 2013 Y. Chae, K. Souri, K.A.A. Makinwa