Print Email Facebook Twitter An Incremental VON-Based Debug System for Commercial FPGA Architecture Title An Incremental VON-Based Debug System for Commercial FPGA Architecture Author Gupta, R.K. Contributor Wong, J.S.S.M. (mentor) Palm, A. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Computer Engineering Programme Embedded Systems Date 2015-12-15 Abstract Electronic companies are increasingly using field-programmable gate arrays in various domains such as application acceleration, complex digital designs or ASIC prototyping. The Verification phase holds a significant place in the FPGA design development process. A key challenge during verification is observability. This is defined as the ability to view all internal states of a circuit. Due to poor observability, a significant portion of designer's effort is spent in this phase, specifically performing the debugging task. A common solution to improve observability is using embedded logic analyzers (ELA) that inserts trace-buffers into the design to record on-chip signal values. When on-chip memory is used for observation it is termed as trace-buffers. This approach has limitations such as slow debug cycles, pre-determining the signals to be traced or using logic resources on FPGA. This work proposes a new debug system for improving the observability while overcoming the limitations of ELAs. The proposed debug system extends a recent technique referred as virtual overlay network (VON) for commercial FPGA device. This network can be perceived as built on top of initial circuit mapping and multiplexes all circuit signals to the on-chip memory for observation. It overcomes the limitation of commercial debug tools based on ELAs. We investigate the factors that inuence the performance of VON for Xilinx Virtex, as it constitutes the core of debug system. We demonstrate that a new bit-stream to program the FPGA connecting hundreds of signals to the on-chip memory can be generated in less than 630 seconds, during debug cycle, for a fairly large circuit having normal re-compilation time of more than 5 hours. The proposed system proves to be a promising way of improving observability and potentially reducing the debug turn time with zero area overhead. Currently, the system is limited to work with Xilinx Virtex family of devices. Subject FPGA VerificationDebuggingOverlay NetworkTrace-Based To reference this document use: http://resolver.tudelft.nl/uuid:c850437b-4f38-4d02-9ec7-a490e78766d6 Part of collection Student theses Document type master thesis Rights (c) 2015 Gupta, R.K. Files PDF MSc-Thesis-GuptaR.K-4329384.pdf 3.01 MB Close viewer /islandora/object/uuid:c850437b-4f38-4d02-9ec7-a490e78766d6/datastream/OBJ/view