Print Email Facebook Twitter Design of a Distributed Clock Generator for Multiple Power Domain System-on-Chip Integrated Circuits Title Design of a Distributed Clock Generator for Multiple Power Domain System-on-Chip Integrated Circuits Author Wan, J. Contributor Long, J. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics & Computer Engineering Date 2008-10-28 Abstract Modern system-on-chip IC designs show great requirement on minimizing power consumptions. One of the low power techniques is using dynamic voltage frequency scaling for each power domain. Yet the clock generator unit is the bottleneck to apply this technique. In this thesis, we focus on the local clock generator unit solution and design three new local clock generators which share the power supply with digital blocks. The best candidate provides good jitter performance (10ps) under large power supply noise, low power consumption (900?W) and small area (90×60?m2). The influence of power supply noise on jitter of each circuit components, like voltage control oscillator, frequency divider, phase frequency detector, charge pump, loop filter and clock buffers are studied in thoroughly. To reference this document use: http://resolver.tudelft.nl/uuid:cbdf86c6-9979-44c5-9f0e-c0bb96bb16d9 Part of collection Student theses Document type master thesis Rights (c) 2008 Wan, J. Files PDF graduation_report_Jinbo_W ... _28_10.pdf 8.58 MB Close viewer /islandora/object/uuid:cbdf86c6-9979-44c5-9f0e-c0bb96bb16d9/datastream/OBJ/view