Towards a fault tolerant RISC-V softcore

Towards a fault tolerant RISC-V softcore

Heida, W.F.

Wong, J.S.S.M. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

2016-08-31

As predicted by Gordon E. Moore in 1975, the number of transistors has doubled every two years over the last decades. This technology scaling led to a higher performance of Integrated Circuits (ICs) like processors, but have also made these devices more susceptible to Single Event Effects (SEEs). SEEs are caused by transistors changing state unintended due to particles disposing significant amounts of energy when they hit an IC. In this thesis, the design, implementation, and verification of a fault tolerant RISC-V processor, which can detect two errors and correct one error, is presented. The RISC-V Instruction Set Architecture (ISA) is an open-source architecture which defines all interactions between the software and hardware. Two designs, the ECC-based and Hybrid design, are presented which both use Error Correction Codes (ECC) and N-Modular Redundancy (NMR) for adding fault tolerance to the softcore. Hamming Single Error Correction, Double Error Detection (SECDED) codes were selected as the ECC coding scheme. The hybrid design, which uses NMR in the pipeline and ECC for memory elements, is chosen for implementation, because it has a lower complexity, less Single Points of Failure (SPOFs) and a higher estimated clock frequency. The design's fault tolerance is verified with fault injection through saboteurs, which are placed at predefined locations in the design. The test architecture for the design consists of a verification suite, a simulation-based environment using ModelSim and an on-board test environment using a Spartan-6 Field Programmable Gate Array (FPGA). The verification tests showed that the hybrid design can mitigate all injected single and double faults, without having a single failure occurring. The design did not meet the clock frequency and resource utilization targets set by Technolution B.V. because of long delay paths and large decoders. The design, however, allows for improvements like the insertion of extra pipeline stages and parallel decoding and data processing

RISC-V softcore
Fault Tolerance
ECC
NMR

http://resolver.tudelft.nl/uuid:cee5e97b-d023-4e27-8cb6-75522528e62d

Student theses

master thesis

(c) 2016 Heida, W.F.