Print Email Facebook Twitter A Reconfigurable Ultrasound Transceiver ASIC With 24 x 40 Elements for 3-D Carotid Artery Imaging Title A Reconfigurable Ultrasound Transceiver ASIC With 24 x 40 Elements for 3-D Carotid Artery Imaging Author Kang, E. (TU Delft Electronic Instrumentation) Ding, Q. (TU Delft Electronic Instrumentation) Shabanimotlagh, M. (TU Delft ImPhys/Acoustical Wavefield Imaging) Kruizinga, P. (Erasmus MC) Chang, Z.Y. (TU Delft Electronic Instrumentation) Noothout, E.C. (TU Delft ImPhys/Acoustical Wavefield Imaging) Vos, H.J. (TU Delft ImPhys/Acoustical Wavefield Imaging; Erasmus MC) Bosch, J.W. (Erasmus MC) Verweij, M.D. (TU Delft ImPhys/Acoustical Wavefield Imaging; Erasmus MC) de Jong, N. (TU Delft ImPhys/Acoustical Wavefield Imaging; Erasmus MC) Pertijs, M.A.P. (TU Delft Electronic Instrumentation) Date 2018 Abstract This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) designed for 3-D ultrasonic imaging of the carotid artery. This application calls for an array of thousands of ultrasonic transducer elements, far exceeding the number of channels of conventional imaging systems. The 3.6 x 6.8 mm² ASIC interfaces a piezo-electric transducer (PZT) array of 24 x 40 elements, directly integrated on top of the ASIC, to an imaging system using only 24 transmit and receive channels. Multiple ASICs can be tiled together to form an even bigger array. The ASIC, implemented in a 0.18 μm high-voltage (HV) BCD process, consists of a reconfigurable switch matrix and row-level receive circuits. Each element is associated with a compact bootstrapped HV transmit switch, an isolation switch for the receive circuits and programmable logic that enables a variety of imaging modes. Electrical and acoustic experiments successfully demonstrate the functionality of the ASIC. In addition, the ASIC has been successfully used in a 3-D imaging experiment. Subject 3-D ultrasound imaginghigh-voltage (HV) switchesmatrix transducerreconfigurabilityultrasound application-specific integrated circuit (ASIC). To reference this document use: http://resolver.tudelft.nl/uuid:d7438b91-9541-4622-b3ba-8b521020ed2d DOI https://doi.org/10.1109/JSSC.2018.2820156 ISSN 0018-9200 Source IEEE Journal of Solid State Circuits, 53 (7), 1-11 Bibliographical note Accepted author manuscript Part of collection Institutional Repository Document type journal article Rights © 2018 E. Kang, Q. Ding, M. Shabanimotlagh, P. Kruizinga, Z.Y. Chang, E.C. Noothout, H.J. Vos, J.W. Bosch, M.D. Verweij, N. de Jong, M.A.P. Pertijs Files PDF Kang_JSSC2018_postprint.pdf 1.98 MB Close viewer /islandora/object/uuid:d7438b91-9541-4622-b3ba-8b521020ed2d/datastream/OBJ/view