Print Email Facebook Twitter A 9-bit 33MHz Hybrid SAR Single-slope ADC Title A 9-bit 33MHz Hybrid SAR Single-slope ADC Author Hu, W. Contributor Pertijs Michiel, A.P. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics & Computer Engineering Programme Micro-electronics Date 2015-12-16 Abstract In this work a 9-bit, 33MHz hybrid SAR single-slope ADC for element-level digitization in 2D ultrasound transducer arrays is presented. This hybrid architecture consists of a 5-bit SAR ADC followed by a 4-bit single-slope ADC. In the comparator design, the dynamic comparator and the continuous-time comparator for the SAR and single-slope conversion, respectively, are combined together with a shared preamplifier. The simulated ENOB is 8.96 bit, the power consumption is 800uW, the estimated area is 0.015mm2 and the achieved FoM is 48.7fJ/conv-step. Subject ADCHybrid SAR single-slope To reference this document use: http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842 Embargo date 2017-01-01 Part of collection Student theses Document type master thesis Rights (c) 2015 Hu, W. Files PDF MSc_thesis_WeihanHu.pdf 2.44 MB Close viewer /islandora/object/uuid:d9773876-5527-473a-a2d0-64cad121a842/datastream/OBJ/view