Fine-Grain Runtime Fault Diagnosis for Reconfigurable Logic Blocks

Fine-Grain Runtime Fault Diagnosis for Reconfigurable Logic Blocks

Tzilis, S.

Sourdis, I. (mentor)
Gaydadjiev, G.N. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

Computer Engineering M.Sc.

2010-06-29

The ever-shrinking technology features have as a direct consequence the increase of defect density in VLSI chips. Going into the nano-scale era, the fabrication procedures cannot keep improving at the pace of the aforementioned shrinking of technology features. Fault Tolerance emerges as a much cheaper solution and it is imperative in the future to be able to build a reliable system with unreliable components. Reconfigurable realization platforms offer the ideal substrate for such approaches, because of their regularity and reconfigurability, which allow for the basic resources to be substitutable, relaxing the defect-free requirement for the whole chip. Sparing and matching techniques allow for substitution and alternative utilization of resources respectively, paving the way to the nano-scale era. Although a significant number of research works have focused on sparing, very few actually go on to reusing the defective resources and even in these cases, the characterization is conservative, sacrificing more functionality than it needs to. We focus on improving the particular drawback, by proposing two distinct methods for high resolution fault diagnosis of reconfigurable logic resources. The methods are based on the function generator and shift register modes of operation of an FPGA slice. We choose to decouple the diagnosis problem from those of fault detection and localization that have been extensively researched and in this way relax the fault coverage requirements for our methods: It is critical to rescue the core functionality of a defective resource with minimal cost, rather than cover 100% of its possible faults. Substitutable Resource Characterization is performed based on the diagnosis result in a modular manner. Both diagnostic testers are prototyped on FPGA and applied to a real Circuit Under Test, with the help of fault injection. The experimental results show that our approach offers the basis for a viable, low-overhead integrated fault tolerance strategy, which we hope to continue developing in the near future.

Fault Tolerance
Fault Diagnosis
Matching
Reconfigurable
Substitutable Resource

http://resolver.tudelft.nl/uuid:de3e099b-e6d0-4a8b-aaab-aefbc1ffd707

Student theses

master thesis

(c) 2010 Tzilis, S.