This thesis gives an insightful analysis of the pinned photodiode 4T CMOS pixel from three different aspects. Firstly, from the charge accumulated aspect, the PPD full well capacity and related parameters of influence are investigated such as the pinning voltage, and transfer gate potential barrier. Secondly, from the charge transfer aspect, the image lag performance of 4T CMOS pixels is characterized and optimized. Thirdly, from the dark signal aspect, the hot carrier effect in the 4T CMOS pixel source follower is characterized and analysed. In Chapter 1, a brief overview of the image sensor development is given. Two types of image sensors are compared: the charge coupled device (CCD) and the complementary metal-oxide-semiconductor (CMOS) image sensor. Since system integration is one of important advantages of CMOS image sensors, the CMOS image sensor is considered from the device, circuit and system level. In this thesis, the research is focused on pixel design at the device level. To further understand and improve the performance of the pixel, two test chips are implemented and a few pixel level parameters are characterized and analysed in this thesis. Chapter 2 introduces the 4T CMOS active pixel. First, the photodiode is presented on the basis of theory and optimization. Next, as an improvement of the photodiode, the pinned photodiode (PPD) is then presented for CMOS image sensor pixel design. The main advantages of the PPD are better noise characteristics, and dark current performance compared with the photodiode. A few important performance specification parameters, e.g. dynamic range, full well capacity, and image lag, are introduced and some of them are discussed further in the following chapters. In Chapter 3, two potential based characterization methods named the pinning voltage measurement and feedforward effect measurement are used to characterize a few potential steps in the PPD-TG-FD structure. To investigate the influence of different pixel design variations in more depth, two test chips with different fabrication processes are implemented which each contain 80 different pixel designs. As an important parameter of the PPD, the pinning voltage of the PPD does not only influence the charge transfer process but also influences the full well capacity. In addition to the pinning voltage, the TG “ON” and “OFF” potential can also influence the charge transfer process and full well capacity. Using the pinning voltage measurement, methods of estimation and extraction the TG “ON” potential and the transfer gate related process parameters such as channel doping concentration and oxide thickness are proposed based on the classic MOS model. The TG “OFF” potential barrier can also be extracted from the feedforward effect measurement without any FD node capacity limitation. From our testchip measurement results it can be found that the TG “OFF” potential barrier is not only determined by the transfer gate low voltage, but can also be influenced by the transfer gate length, width, and FD node reset voltage in certain design and process cases. With both the pinning voltage and transfer gate potential barrier characterization, the full well capacity of the PPD is discussed further in this chapter. Chapter 4 is focused on image lag performance. To optimize the image lag performance of the large photodiode, in addition to the transfer gate potential barrier optimization, changing the photodiode shape can also help to speed up the charge transfer process without changing the manufacturing process. A few different photodiode shapes are implemented for image lag optimization. Along with the photodiode optimization, the influence of the transfer gate dimension, voltage and FD node on the image lag are also discussed in this chapter. A “T” shape transfer gate pixel design of the test chip is verified, which can increase the charge transfer efficiency of the pixel. From the measurement result it can be found that a longer transfer gate does not necessarily achieve a lower image lag. The transfer gate length can also influence the floating diffusion capacity. The potential of transferred electrons in the FD node will influence the lag after the charge transfer process. In Chapter 5, the hot carrier mechanism induced dark signal is investigated based on the 4T pixel. As with the hot carrier mechanism in the MOSFET, the source follower and transfer gate in the 4T pixel have the possibility of inducing hot carrier injection in certain process, design and application cases. In our test chip, the hot carrier injection can be found in the nMOS source follower. In the same testchip, replacing the nMOS source follower with a pMOS can prevent the hot carrier effect. Based on further measurement results, the 4T pixel hot carrier effect dependency on the voltage, current and temperature are presented, which can also confirm the hot carrier injection occurrence in the test structure. Chapter 6 summarizes the main work in this thesis based on three different aspects. Furthermore, some proposals are given for the possible research considerations for future work in this field.