Print Email Facebook Twitter Through-polymer via (TPV) and method to manufacture such a via Title Through-polymer via (TPV) and method to manufacture such a via Author Poelma, R.H. Van Zeijl, H. Zhang, G. Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics Date 2014-07-10 Abstract The invention relates to vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers. In particular, the invention relates to a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers i.e. in an out-of-plane direction. To reference this document use: http://resolver.tudelft.nl/uuid:e19b1fa2-9500-40a9-bf35-4501e319ab56 Publisher European Patent Office Source http://worldwide.espacenet.com/publicationDetails/biblio?DB=EPODOC&II=13&ND=3&adjacent=true&locale=en_EP&FT=D&date=20140710&CC=WO&NR=2014107108A1&KC=A1 Source WO 2014107108 (A1) Part of collection Institutional Repository Document type patent Rights (c) 2014 The Author(s) Files PDF WO2014107108A1.pdf 727.8 KB Close viewer /islandora/object/uuid:e19b1fa2-9500-40a9-bf35-4501e319ab56/datastream/OBJ/view