Self-timed interconnect for SNN - From Point to Point Communication to Multi-array Segmented-bus Solution

Self-timed interconnect for SNN - From Point to Point Communication to Multi-array Segmented-bus Solution

Zhang, Jinyao (TU Delft Electrical Engineering, Mathematics and Computer Science)

van Leuken, T.G.R.M. (mentor)
Mandloi, N.K. (graduation committee)

Delft University of Technology

Electrical Engineering | Circuits and Systems

2022-11-30

Spiking Neural Networks use Address Event Representation to communicate among different Neuron Arrays. To mimic the behavior of the human neural system and meets the requirement for large Neuron Array communication, the AER interconnect should be area-saving, have low power, and operates at high speed.
This thesis aims to build self-timed interconnects for point-to-point and multi-array communication. The whole system is designed at the RTL level using SystemVerilog. For point-to-point communication, two transmitters are implemented and compared according to their synthesis results. In the multi-array communication structure, we develop a generalized segmented-bus topology and the element - Fence to control its segments. Different timing problems in the design are analyzed, and corresponding solutions are proposed. The whole system can operate at around 1Gbps in a self-timed manner without
any timing problems.

SNN
self-timed circuit
interconnect
timing

http://resolver.tudelft.nl/uuid:e42e23b7-97e6-423c-b5bb-acb959e25a2e

Student theses

master thesis

© 2022 Jinyao Zhang