Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

Title

Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

Author

Wang, B.

Contributor

Staszewski, R.B. (mentor)
Liu, Y.H. (mentor)

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics & Computer Engineering

Programme

Master of Microelectronics

Date

2014-01-14

Subject

DTC
TDC
ADPLL
ultra-low power
CMOS

To reference this document use:

http://resolver.tudelft.nl/uuid:ea10ff84-a257-4712-b9ab-8cdf13b23a4d

Embargo date

2016-05-01

Part of collection

Student theses

Document type

master thesis

Rights

(c) 2014 Wang, B.