A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs

Planar scaling of semiconductor ICs for achieving higher integration seems to be on the brink of saturation. As an alternative solution, three-dimensional (3D) integration follows a more than Moore strategy in which circuit layers are stacked vertically. Although, 3D integration technology has moved from Lab to Fab, a complete supply chain is yet to fall in place. Due to the lack of a fully automated 3D IC design flow, realistic performance estimation at an early stage becomes imperative to ensure an efficient end-to-end design cycle. In this paper, an approach is shown for early performance and cost estimation of a 3D stacked IC in order to allow critical technology parameters to influence system design decisions. A novel methodology is proposed which explores Through-Silicon-Via (TSV) placement topologies for a 2-tier vertical interconnect across two performance corners of the TSV technology. It estimates electrical performance and TSV area penalty which are then translated to system design metrics. The methodology is applicable to digital ICs and offers flexibility in selection of the CMOS technology node and the 3D stacking granularity. Its implementation in SystemC efficiently achieves parameterizability and enables its integration into a high-level system simulation framework. By applying the methodology to a case of a 7-port 3D router it was found that, the most preferred TSV placement topology in terms of performance and cost is Isolated for 45 nm technology node and Shielded for 32 nm technology node.

Subject

3D IC
TSV
SystemC
simulation methodology
interconnect topology
3D chip stacking
TSV modeling

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http://resolver.tudelft.nl/uuid:ec523897-4480-438f-8558-a72636b33dbc

Embargo date

2011-09-24

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Student theses

Document type

master thesis

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RadhikaJ_MSc_Thesis.pdf

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